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Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
Patch Set 14:
(3 comments)
File src/mainboard/clevo/cml-u/Kconfig:
PS13:
> Please do that in a separate change.
ugh, this wasn't planned o.O
File src/mainboard/clevo/tgl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/59548/comment/4957106b_9a65cc06
PS12, Line 57: config VARIANT_DIR
: default "l140mu" if BOARD_CLEVO_L140MU
> I know, it also needs a little cleanup.
agreed
File src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/59548/comment/47a8c0c1_5ea583a3
PS12, Line 10: PAD_NC(GPP_C22, UP_20K),
: PA
> I know, I would do the same for L140CU too. […]
Ack
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Michał Żygowski, Michał Kopeć, Paul Menzel, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59548
to look at the new patch set (#14).
Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
mb/clevo/tgl-u: add new board L14xMU
Add new board Clevo L14xMU (TGL).
GPIOs were configured based on schematics.
Tested and working:
- On-board RAM (M471A1G44AB0-CWE)
- DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
- Graphics (GOP driver), including HDMI
- Keyboard
- I2C touchpad (including interrupt)
- TPM (with interrupt on Windows, only polling on Linux [1])
- microSD Card reader
- both NVME ports
- Speakers
- Microphone
- Camera
- WLAN/BT (CNVi)
- All USB2/3 ports including Type-C
- Thunderbolt detects my work laptop in TB Control Center
(I couldn't test anything more due to security policy.)
- TianoCore
- internal flashing with flashrom on vendor firmware
Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:
1) Boot vendor firmware once to let it disable PTT via CSME firmware
feature override.
2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
disabled.
Boots fine:
- Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
- Windows 10 21H2 (Build 19044.1586)
Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA
- 3G/LTE
- 3G/LTE depends on mising EC driver
- tested board is non-LTE version with a second NVME port instead
- LTE version has a USB-only M.2 slot (supported by this port)
Doesn't work:
- TPM interrupt on Linux [1]
- WLAN/BT (PCIe) - gets detected but can't be enabled
- All EC related functions - EC driver is WIP
- Fn-Keys
- S0ix
- UCSI
- Fan control
- Battery info
[1] https://lkml.org/lkml/2021/5/1/103
Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
A src/mainboard/clevo/tgl-u/Kconfig
A src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/Makefile.inc
A src/mainboard/clevo/tgl-u/board_info.txt
A src/mainboard/clevo/tgl-u/bootblock.c
A src/mainboard/clevo/tgl-u/cmos.default
A src/mainboard/clevo/tgl-u/cmos.layout
A src/mainboard/clevo/tgl-u/dsdt.asl
A src/mainboard/clevo/tgl-u/include/variant/gpio.h
A src/mainboard/clevo/tgl-u/include/variant/ramstage.h
A src/mainboard/clevo/tgl-u/include/variant/romstage.h
A src/mainboard/clevo/tgl-u/ramstage.c
A src/mainboard/clevo/tgl-u/romstage.c
A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex
A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc
A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt
A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt
A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c
A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c
A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c
A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c
23 files changed, 893 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/14
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Change subject: device/pci_device.c: Return if the scan parameter is invalid
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63127 )
Change subject: soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE
......................................................................
soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE
The Sabrina microcode update files are 3200 bytes large and not 5568
like it is the case on Cezanne where this file was originally copied
from.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/soc/amd/sabrina/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 8392e2f..bef4160 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -87,7 +87,7 @@
default n
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
- default 5568
+ default 3200
config CHIPSET_DEVICETREE
string
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63143 )
Change subject: soc/intel/common/acpi: Add SPC0 and GPC0 methods
......................................................................
Set Ready For Review
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Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
Patch Set 13: Code-Review+1
(3 comments)
File src/mainboard/clevo/cml-u/Kconfig:
PS13:
Please do that in a separate change.
File src/mainboard/clevo/tgl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/59548/comment/54f13cd2_9c1f79a7
PS12, Line 57: config VARIANT_DIR
: default "l140mu" if BOARD_CLEVO_L140MU
> this file is mostly a copy of l140cu^^ I agree that it fits better near the mainboard dir, though. […]
I know, it also needs a little cleanup.
File src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/59548/comment/d7180565_cda318a8
PS12, Line 10: PAD_NC(GPP_C22, UP_20K),
: PA
> first, it's the same as l140cu here. […]
I know, I would do the same for L140CU too. I just would like to keep it minimal and it's not strictly needed to configure them as NC here. Not sure why we did it for L140CU.
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63141 )
Change subject: soc/intel/alderlake/pmc_descriptor.c: Don't depend on FMAP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Sridhar, do you think the ADLRVP build still required the A0 PMC descriptor change as well? Can we j […]
Tim, ADLRVP also doesn't require A0 PMC descriptor change. Agree, we can drop the code from coreboot itself. I will push the CL for the same. Thanks!
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Change subject: Docs/project_ideas: Make coreboot ARM BBR compliant
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63034/comment/e8da2ee2_4d71e75b
PS2, Line 7: Make coreboot ARM BBR compliant
Please update accordingly as per Julius' comment
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Change subject: mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt
......................................................................
Patch Set 4: Code-Review-1
(1 comment)
File src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/63132/comment/f4cc114f_68a941ed
PS4, Line 16: SPD_SOURCES += $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/K4U6E3S4AB-MGCL.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL
> Is there no way to update the memory_parts. […]
+1. As is, this will get overwritten every time part_id_gen is run. We could modify apcb_v3_edit.py to inject the part number at this index. Alternatively, we could modify part_id_gen to support special spd binaries.
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Change subject: soc/amd/sabrina: Add espi_switch_to_spi2_pads
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63095/comment/184eeab4_b7137f86
PS4, Line 7: 2
same here
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