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Change subject: libpayload: Parse the ACPI RSDP table entry
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Patch Set 7: Code-Review+2
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Change subject: soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
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Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
......................................................................
Patch Set 5:
(1 comment)
File util/sconfig/main.c:
https://review.coreboot.org/c/coreboot/+/51180/comment/bbb9fc9a_5f7845a7
PS5, Line 1344: extern DEVTREE_CONST struct device *const __pci_%d_%02x_%d
> Does this make sense? You'd sort of expect this to be a PCI's BDF but that's not the case with the m […]
We need something that will distinguish devices on different domains - so why not use domain number here (meybe move before "pci" in name? or use another flag to mark it is domain and not bus)
We only have root buses here and parent is domain. So it is more like "DDF"("D"omain, root bus "D"evice and "F"unction) than full pci BDF in variable name to prevent name conflict. It is early "static" stage when we don`t have final pci root bus numbers that could be used instead of domain numbers.
ptr->parent->dev->path_a == 0 means first domain - so using this we will prevent adding devices from other domain defined in devicetree so reverting what this patch was for.
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Change subject: mb/google/skyrim: Disable PSP postcodes
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63119/comment/96df3519_043c0b16
PS3, Line 8:
> Why?
Done
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Change subject: soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63122/comment/18b73dd9_cee8d66d
PS1, Line 7: Donot
> Do not
Done
https://review.coreboot.org/c/coreboot/+/63122/comment/537eb155_7ab4ab33
PS1, Line 8:
> Why? What problem does it fix, and where is that documented?
Done
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Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63118/comment/f5e0cab5_b119c358
PS2, Line 12:
> Are AMD’s SMU folks aware of that problem?
Done. b/227201571
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Change subject: mb/google/skyrim: Disable PSP postcodes
......................................................................
mb/google/skyrim: Disable PSP postcodes
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
---
M src/mainboard/google/skyrim/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63119/5
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Change subject: soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
......................................................................
soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
---
M src/soc/amd/sabrina/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63122/3
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Change subject: mb/google/skyrim: Disable PSP postcodes
......................................................................
mb/google/skyrim: Disable PSP postcodes
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
---
M src/mainboard/google/skyrim/Kconfig
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63119/4
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Change subject: soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode
......................................................................
soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
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