coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by Kyösti Mälkki (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Tim Wawrzynczak, Julius Werner. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58896 ) Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... Patch Set 13: (1 comment) File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/58896/comment/35dcb330_1c46e61d PS7, Line 67: } > Okay, great... honestly then I'd say just rip this out and leave it to depthcharge. […] Case of S3 resume path is addressed with line 47, right? Julius, are you suggesting that on entry to payload CNVS does not need to have valid vbt2 field? I would rather do that as a followup if that is what you mean. I have always thought some CNVS fields might have uses with other payloads, but cannot tell for sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 20:44:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeoS: Retain ACPI CNVS contents on S3 resume
by Kyösti Mälkki (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Tim Wawrzynczak, Julius Werner. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61619 ) Change subject: ChromeoS: Retain ACPI CNVS contents on S3 resume ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > so this would be sarien and arcada then? those should be the only devices that would have ChromeOS G […] Also the boards in CB:58896 were affected, for S3 resume path ECFW_RO is unconditionally set, while normal boot path might have had ECFW_RW in GNVS. -- To view, visit https://review.coreboot.org/c/coreboot/+/61619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea71a51aba7ab1b6966389c17a1e06ccc96ae0e9 Gerrit-Change-Number: 61619 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 20:38:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree for moli
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: YH Lin, Subrata Banik, Eric Lai, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63080 ) Change subject: mb/google/brask/variants/moli: update overridetree for moli ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63080/comment/68a78674_b82aa45d PS7, Line 8: option STORAGE_NVME 0 : option STORAGE_EMMC 1 Are these going to be used to enable / disable devices ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 7 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 28 Mar 2022 20:08:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Maulik V Vaghela. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/alderlake/retimer.c: https://review.coreboot.org/c/coreboot/+/59666/comment/ba1f135e_3c7b0d48 PS16, Line 19: for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { : if (i == typec_port) { : > hmm, typec_port 0 will always be mapped to ec port 0, even when tcss port 0 (tcss_usb3_port1) is dis […] Oh yeah I see, maybe it shoiuld be like ``` for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { if (!is_dev_enabled(tcss_port_arr[i])) continue; if (i == typec_port) { printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, ec_port); return ec_port; } ec_port++; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 16 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 20:07:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Sean Rhodes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/tigerlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/58798/comment/d1a0d349_6be1a549 PS14, Line 159: Software Connection Manager doesn't work with Linux 5.13 or later > I don't get it - what is the reason for that? I'm not that familiar with USB4/TB3 yet, but from what […] Firmware connection manager refers to the IOM firmware IIUC (Intel blob for handling Type-C ports) -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 28 Mar 2022 19:59:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: Add FlameGraph-compatible timestamps output
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jakub Czapiga, Paul Menzel, Alex Levin, Julius Werner, Jan Dabros. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62474 ) Change subject: util/cbmem: Add FlameGraph-compatible timestamps output ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 Gerrit-Change-Number: 62474 Gerrit-PatchSet: 15 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 19:56:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/timestamp_serialized: Add timestamp enum to name mapping
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jakub Czapiga, Julius Werner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62709 ) Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Gerrit-Change-Number: 62709 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 19:54:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/bsd/helpers: Remove redundancy with libpayload defines
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jakub Czapiga, Julius Werner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62921 ) Change subject: commonlib/bsd/helpers: Remove redundancy with libpayload defines ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: Couldn't this impact any payloads though that don't have the right headers (commonlib/bsd/helpers.h) for ALIGN, etc. ? -- To view, visit https://review.coreboot.org/c/coreboot/+/62921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Gerrit-Change-Number: 62921 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 19:52:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Subrata Banik, John Zhao, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62723/comment/21bd107c_0ee44e5a PS11, Line 872: : /* Fill platform pad configuration and authentication functions */ : config->common_soc_config.tcss_ops.configure_aux_bias_pads = : tcss_configure_aux_bias_pads_regbar; : config->common_soc_config.tcss_ops.valid_tbt_auth = tcss_valid_tbt_auth; WDYT about assigning these function pointers in `soc_init_pre_device()` from chip.c instead, before even calling into `fsp_silicon_init()`? File src/soc/intel/common/block/usb4/usb4.c: https://review.coreboot.org/c/coreboot/+/62723/comment/31f2492e_84b858a0 PS11, Line 34: if (config->tcss_ops.valid_tbt_auth) { : if (!config->tcss_ops.valid_tbt_auth()) : return; : } > > It seems logically clear NOT to combine them together. […] `&&` is explicitly lazy, so ``` if (config->tcss_ops.valid_tbt_auth && !config->tcss_ops.valid_tbt_auth()) return; ``` will work -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 11 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 19:48:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Tim Wawrzynczak (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/62987/comment/f641ee34_56686f22 PS7, Line 111: die Sorry I mean this, here, is it really worth halting boot here because of this? -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 19:42:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022