coreboot-gerrit March 2022

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jett Rink (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jes Klinke, Christian Walter, Julius Werner. Jett Rink has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... Patch Set 1: (1 comment) File src/drivers/spi/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/63158/comment/65127366_ce799655 PS1, Line 515: if (tpm_first_access_this_boot()) { … [View More]

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Change in coreboot[master]: ec/starlabs/merlin: Make ITE files dependent on Kconfig
by Sean Rhodes (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62677 ) Change subject: ec/starlabs/merlin: Make ITE files dependent on Kconfig ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: If by any chance you have a spare 5 minutes :) -- To view, visit https://review.coreboot.org/c/coreboot/+/62677 To unsubscribe, or for help … [View More]

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Change in coreboot[master]: soc/intel/apollolake: Add support for Measured Boot with PTT
by Sean Rhodes (Code Review) 28 Mar '22

28 Mar '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61386 ) Change subject: soc/intel/apollolake: Add support for Measured Boot with PTT ...................................................................... Abandoned Overcomplicated.. -- To view, visit https://review.coreboot.org/c/coreboot/+/61386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 28 Mar '22

28 Mar '22

Jes Klinke has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... tpm: Accept Google Ti50 TPM DID:VID A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk(a)… [View More]chromium.org> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c 3 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63158/1 diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 800d145..47924ee 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -17,6 +17,7 @@ const char *device_name; } dev_map[] = { {0x1ae0, 0x0028, "CR50"}, + {0x6666, 0x50a4, "TI50"}, {0xa13a, 0x8086, "Intel iTPM"} }; diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 7eb066d..ffb0762 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -36,6 +36,7 @@ #define CR50_TIMEOUT_NOIRQ_MS 20 /* Timeout for TPM ready without IRQ */ #define CR50_TIMEOUT_IRQ_MS 100 /* Timeout for TPM ready with IRQ */ #define CR50_DID_VID 0x00281ae0L +#define TI50_DID_VID 0x504a6666L struct tpm_inf_dev { int bus; @@ -455,7 +456,7 @@ rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4); /* Exit once DID and VID verified */ - if (!rc && (*did_vid == CR50_DID_VID)) { + if (!rc && (*did_vid == CR50_DID_VID || *did_vid == TI50_DID_VID)) { printk(BIOS_INFO, "done! DID_VID 0x%08x\n", *did_vid); return 0; } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 43fd933..af79990 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -419,6 +419,7 @@ /* Device/vendor ID values of the TPM devices this driver supports. */ static const uint32_t supported_did_vids[] = { 0x00281ae0, /* H1 based Cr50 security chip. */ + 0x504a6666, /* H1 based Ti50 security chip. */ 0x0000104a /* ST33HTPH2E32 */ }; @@ -507,6 +508,16 @@ cr50_set_board_cfg(); } } + /* Do some ti50-specific things here. */ + if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x6666 && tpm_info.device_id == 0x504a) { + struct cr50_firmware_version ver; + + if (tpm_first_access_this_boot()) { + /* This is called for the side-effect of printing the firmware version + string */ + cr50_get_firmware_version(&ver); + } + } return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: lib: Add a mutex
by Kyösti Mälkki (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Raul Rangel, Nico Huber, Xiang W, Philipp Hug, Jonathan Neuschäfer, Tim Wawrzynczak, Angel Pons, Rob Barnes, Karthik Ramasubramanian. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: > Well, I'm not sure what more to say here. […] All this review is … [View More]happening in a no-op change, while CB:59321 is where spinlock/mutex change really takes place. It has not been rebased for couple months. I have provided pointers in my previous commentary (CB:60253 and CB:60280) that show it's easy to use compiler atomic builtins to provide a spinlock, and easy to build mutex with such a spinlock. It's unreviewed work that I still consider viable alternative solution, and a cleaner one. It does not answer riscv spinlocks either, it's incomplete work. I don't agree with Julius that removing spinlock and only providing mutex would simplify codebse. We continue to have sequences where, IMHO spinlock makes more sense than newly introduced mutex. This is known to not be SMP safe, as it turns out it completely lacks a spinlock currently, but why is mutex() ever better than spinlock() around a index/data IO access like these: src/arch/x86/include/arch/pci_io_cfg.h The case is somewhat the same with RTC / CMOS NVRAM access using split index/data IO access. Seems like those cmos_read/write() variants are currently SMP -safe either. CB:34929 hints that there is more work to be done on this area and talks about .data, while .bss seems to be the easier approach. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 15 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 21:29:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment [View Less]

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Change in coreboot[master]: mb/clevo/tgl-u: add new board L14xMU
by Angel Pons (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Michał Kopeć, Paul Menzel, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb/clevo/tgl-u: add new board L14xMU ...................................................................... Patch Set 15: Code-Review+1 (2 comments) File src/mainboard/clevo/tgl-u/Kconfig: https://review.coreboot.org/c/coreboot/+/59548/comment/… [View More]7f7bcf8c_7f5b4f2a PS13, Line 12: select MAINBOARD_HAS_LPC_TPM > well, we have no means making that selectable for the user atm. […] Ack File src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59548/comment/3d7572d1_454e9c9f PS14, Line 191: device ref peg on > > why? it's a SSD slot like pcie_rp9, so grouping them makes more sense to me […] Yeah, it's because I'd expect PEG RPs to come before PCH PCIe RPs. I don't care enough about it though. -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 28 Mar 2022 21:26:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment [View Less]

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Change in coreboot[master]: mb/clevo/tgl-u: add new board L14xMU
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Michał Kopeć, Paul Menzel, Angel Pons, Michael Niewöhner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb/clevo/tgl-u: add new board L14xMU ...................................................................... Patch Set 15: Code-Review+2 (1 comment) File src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb: https://review.coreboot.… [View More]

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by Michael Niewöhner (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Maulik V Vaghela. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/alderlake/retimer.c: https://review.coreboot.org/c/coreboot/+/59666/comment/53da7ef1_dbc1a97b PS16, Line 19: for (uint8_t i = … [View More]

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Furquan Shaikh, Martin Roth, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 5: (1 comment) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/51180/comment/… [View More]6543e332_ed5aad15 PS5, Line 1344: extern DEVTREE_CONST struct device *const __pci_%d_%02x_%d > We need something that will distinguish devices on different domains - so why not use domain number here (meybe move before "pci" in name? or use another flag to mark it is domain and not bus) > We only have root buses here and parent is domain. So it is more like "DDF"("D"omain, root bus "D"evice and "F"unction) than full pci BDF in variable name to prevent name conflict. It is early "static" stage when we don`t have final pci root bus numbers that could be used instead of domain numbers. > ptr->parent->dev->path_a == 0 means first domain - so using this we will prevent adding devices from other domain defined in devicetree so reverting what this patch was for. This is only about exposing devices in a convenient way so that you can for instance directly reference '__pci_1_0_0' from the coreboot source. Without that it's still there in the linked list and you can appropriately find and use it. If you don't know the real bus (eg in early stages) and have not set it there is no point in trying the access this device, so also no point to try to expose it conveniently. -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 5 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 21:07:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment [View Less]

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Michael Niewöhner (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Sean Rhodes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/tigerlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/58798/comment/f9f199c6_99349ce7 PS14, Line 159: Software Connection Manager doesn't … [View More]

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coreboot-gerrit March 2022