coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
by 9elements QA (Code Review) 28 Mar '22

28 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63008 ) Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/97535 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/97534 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/97533 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/97532 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/97531 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/97530 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/97529 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/97528 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/97527 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/97526 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/97525 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/97524 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Gerrit-Change-Number: 63008 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 12:53:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define Kconfigs for Descriptor Region
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Sridhar Siricilla. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62263 ) Change subject: soc/intel/alderlake: Define Kconfigs for Descriptor Region ...................................................................... Patch Set 5: (2 comments) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/62263/comment/6044eaca_65e72961 PS5, Line 372: string "Descriptor Region name" this should not be user visible. https://review.coreboot.org/c/coreboot/+/62263/comment/24d47f03_6f1d400c PS5, Line 371: config SI_DESC_REGION : string "Descriptor Region name" : default "SI_DESC" : help : Name of Descriptor Region in the FMAP : : config SI_DESC_REGION_SZ : int : default 4096 : help : Size of Descriptor Region in the FMAP Why are those in soc/intel/alderlake? It's not alderlake specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/62263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77 Gerrit-Change-Number: 62263 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 12:48:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63009 ) Change subject: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig ...................................................................... soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig This patch uses the FSP event handler feature and updates with coreboot native debug implementation to unify the debug library between coreboot and FSP. BUG=b:225544587 TEST=Able to build and boot Brya with the same FSP debug log before and with this code changes. Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 38415e6..37c0b62 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -42,6 +42,7 @@ select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_USES_CB_DEBUG_EVENT_HANDLER select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP -- To view, visit https://review.coreboot.org/c/coreboot/+/63009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Gerrit-Change-Number: 63009 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63008 ) Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S ...................................................................... soc/intel/alderlake: Use coreboot native event handler for FSP-M/S This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4a27cb5..bd2c0be 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/api.h> +#include <fsp/fsp_debug_event.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <option.h> @@ -509,6 +510,8 @@ static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) + s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); /* PCH UART selection for FSP Debug */ s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2a02c21..2e76cd7 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -6,6 +6,7 @@ #include <cpu/intel/cpu_ids.h> #include <device/device.h> #include <drivers/wifi/generic/wifi.h> +#include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> @@ -364,6 +365,11 @@ { const struct soc_intel_alderlake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) + arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); config = config_of_soc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Gerrit-Change-Number: 63008 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Eric Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63008 ) Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Gerrit-Change-Number: 63008 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 12:25:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63009 ) Change subject: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: > Like to share one observation before we enable this feature on ADL. > > Currently we have fixed size cbmem console which is 8K in size and for sure not enough to hold the entire FSP-M debug log (after the CL gets landed). Typically, FSP-M debug log is very detailed and size is significantly high and I'm afraid we might not able to accommodate the same inside `cbmem -c`. I have verified that we are able to contain entire ramstage log inside `cbmem -c` with FSP debug enabled. > > config PRERAM_CBMEM_CONSOLE_SIZE > hex > default 0x2000 If that overflows coreboot will simply stop filling that log. Debugging most issues in romstage require a hardware console anyway (memory not working) so I think that this is fine for early stages. It's like that for most platforms already. If you have enough CAR you could however try to increase it if you really want that log in memory. -- To view, visit https://review.coreboot.org/c/coreboot/+/63009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Gerrit-Change-Number: 63009 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 12:24:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig
by Eric Lai (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63009 ) Change subject: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Or just partial level of log in the cbmem? I think 2M is too large for the 16M ROM size on small core CPU. -- To view, visit https://review.coreboot.org/c/coreboot/+/63009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Gerrit-Change-Number: 63009 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 28 Mar 2022 12:11:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Clear the whole byte of EFS_GEN
by Bao Zheng (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63138 to review the following change. Change subject: amdfwtool: Clear the whole byte of EFS_GEN ...................................................................... amdfwtool: Clear the whole byte of EFS_GEN Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/63138/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f0fdd0a..0cfe307 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1785,6 +1785,7 @@ amd_romsig->imc_entry = 0; amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0; + amd_romsig->efs_gen.reserved = 0; if (soc_id != PLATFORM_UNKNOWN) { retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, -- To view, visit https://review.coreboot.org/c/coreboot/+/63138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Gerrit-Change-Number: 63138 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig
by Subrata Banik (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63009 ) Change subject: soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Like to share one observation before we enable this feature on ADL. Currently we have fixed size cbmem console which is 8K in size and for sure not enough to hold the entire FSP-M debug log (after the CL gets landed). Typically, FSP-M debug log is very detailed and size is significantly high and I'm afraid we might not able to accommodate the same inside `cbmem -c`. I have verified that we are able to contain entire ramstage log inside `cbmem -c` with FSP debug enabled. config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x2000 -- To view, visit https://review.coreboot.org/c/coreboot/+/63009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Gerrit-Change-Number: 63009 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 11:48:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in blobs[master]: Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215...
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/63097 ) Change subject: Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10" ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Do you mean we need to do version control in coreboot dirvers? […] @hung-te and @yu-ping, do you have any suggestion for this? -- To view, visit https://review.coreboot.org/c/blobs/+/63097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I63923188b814f0b44690784b55bcec9aff9b3d23 Gerrit-Change-Number: 63097 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 11:33:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2022