coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/variants/crota: Add memory config for crota
by Terry Chen (Code Review) 28 Mar '22

28 Mar '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63137 ) Change subject: mb/google/brya/variants/crota: Add memory config for crota ...................................................................... mb/google/brya/variants/crota: Add memory config for crota Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 --- M src/mainboard/google/brya/variants/crota/Makefile.inc A src/mainboard/google/brya/variants/crota/memory.c 2 files changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/63137/1 diff --git a/src/mainboard/google/brya/variants/crota/Makefile.inc b/src/mainboard/google/brya/variants/crota/Makefile.inc index 6c29346..7d1f886 100644 --- a/src/mainboard/google/brya/variants/crota/Makefile.inc +++ b/src/mainboard/google/brya/variants/crota/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/crota/memory.c b/src/mainboard/google/brya/variants/crota/memory.c new file mode 100644 index 0000000..539a486 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 36, 35, 35, 35 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, }, + .dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, }, + }, + .ddr2 = { + .dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, }, + .dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, }, + }, + .ddr3 = { + .dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, }, + .dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, }, + .dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, }, + }, + .ddr5 = { + .dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, }, + .dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, }, + }, + .ddr6 = { + .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, }, + .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Gerrit-Change-Number: 63137 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE
by Fred Reitberger (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63127 ) Change subject: soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 Gerrit-Change-Number: 63127 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 28 Mar 2022 11:32:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC
by John Su (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Derek Huang. John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63116 ) Change subject: mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63116/comment/60c0f54c_7850b70c PS2, Line 9: updated schematics > If they have a version string, please add it. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Gerrit-Change-Number: 63116 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 10:31:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC
by John Su (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: John Su, Tim Wawrzynczak, Derek Huang. Hello Frank Wu, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Eric Lai, Derek Huang, Derek Huang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63116 to look at the new patch set (#3). Change subject: mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC ...................................................................... mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC Configure GPIO according to b:224107199 comment#15. - GPP_E19 from NF to NC. BUG=b:224107199 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b --- M src/mainboard/google/brya/variants/felwinter/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63116/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Gerrit-Change-Number: 63116 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Fix pmif setting for low power mode
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63089 ) Change subject: soc/mediatek/mt8186: Fix pmif setting for low power mode ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63089/comment/e6006f0f_ca6d1c67 PS3, Line 10: which is causing suspend failure > How does it fail exactly? I add this message in commit message. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. -- To view, visit https://review.coreboot.org/c/coreboot/+/63089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Gerrit-Change-Number: 63089 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 10:21:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Fix pmif setting for low power mode
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63089 to look at the new patch set (#4). Change subject: soc/mediatek/mt8186: Fix pmif setting for low power mode ...................................................................... soc/mediatek/mt8186: Fix pmif setting for low power mode The current pmif register setting for low power mode is incorrect, which is causing suspend failure. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode() to correct the setting. This implementation is based on chapter 3.7 in MT8186 Functional Specification. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Zhiyong Tao <zhiyong.tao(a)mediatek.com> Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/pmif.h M src/soc/mediatek/mt8186/mt6366.c A src/soc/mediatek/mt8186/pmif.c 5 files changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63089/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Gerrit-Change-Number: 63089 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in blobs[master]: Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215...
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/63097 ) Change subject: Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10" ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Should coreboot detect, if this firmware version is used, and notify the user? Do you mean we need to do version control in coreboot dirvers? If we want to add this version number in coreboot driver, is it a good idea? Or do we have some example before? -- To view, visit https://review.coreboot.org/c/blobs/+/63097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I63923188b814f0b44690784b55bcec9aff9b3d23 Gerrit-Change-Number: 63097 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 10:15:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63109 ) Change subject: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO" ...................................................................... Patch Set 8: (2 comments) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/63109/comment/7be4ac59_4e750fc4 PS7, Line 138: printk(BIOS_INFO, "DRAM-K: not support USE_CBMEM_DRAM_INFO\n"); > Looks more like a debug message? Done https://review.coreboot.org/c/coreboot/+/63109/comment/2a5247d3_aeeca2a5 PS7, Line 138: not support USE_CBMEM_DRAM_INFO > Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Gerrit-Change-Number: 63109 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 10:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63114 ) Change subject: soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de Gerrit-Change-Number: 63114 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Mar 2022 10:12:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"
by Rex-BC Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63109 to look at the new patch set (#8). Change subject: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO" ...................................................................... soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO" The memory initialization reference code didn't support returning DRAM information in the old platforms, for example MT8192 and MT8195. So we have to add a new configuration USE_CBMEM_DRAM_INFO to make sure the common code will try to get DRAM information on new platforms supporting that. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/memory.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/63109/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Gerrit-Change-Number: 63109 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022