coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Kane Chen. Hello Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63169 to look at the new patch set (#2). Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... soc/intel/common: Update CSE sub partition update The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 33 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63169/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Michael Niewöhner (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/fsp2_0/fsp_timestamp.c: https://review.coreboot.org/c/coreboot/+/62942/comment/1f792870_f41c0bc9 PS6, Line 82: |P add a space, please -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63169 ) Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... soc/intel/common: Update CSE sub partition update The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 33 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63169/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 2756814..d86c41d 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cpu.h> #include <console/console.h> #include <cbfs.h> #include <commonlib/region.h> @@ -9,7 +10,6 @@ #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/intel/common/reset.h> -#include <arch/cpu.h> #define BPDT_HEADER_SZ sizeof(struct bpdt_header) #define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) @@ -779,15 +779,42 @@ } } -static bool cse_sub_part_get_target_rdev(struct region_device *target_rdev, - const char *region_name, enum bpdt_entry_type type) +static bool cse_locate_area_as_rdev_rw(const struct cse_bp_info *cse_bp_info, const char *region_name, + struct region_device *cse_rdev) +{ + struct region_device cse_region_rdev; + size_t size; + uint32_t start_offset; + uint32_t end_offset; + + if (!cse_get_rw_rdev(&cse_region_rdev)) + return false; + + if (!strcmp(region_name, "RO")) + cse_get_bp_entry_range(cse_bp_info, RO, &start_offset, &end_offset); + else + cse_get_bp_entry_range(cse_bp_info, RW, &start_offset, &end_offset); + + size = end_offset + 1 - start_offset; + + if (rdev_chain(cse_rdev, &cse_region_rdev, start_offset, size)) + return false; + + printk(BIOS_DEBUG, "cse_lite: CSE %s partition: offset = 0x%x, size = 0x%x\n", region_name, + (uint32_t)start_offset, (uint32_t) size); + + return true; +} + +static bool cse_sub_part_get_target_rdev(const struct cse_bp_info *cse_bp_info, + struct region_device *target_rdev, const char *region_name, enum bpdt_entry_type type) { struct bpdt_header bpdt_hdr; struct region_device cse_rdev; struct bpdt_entry bpdt_entries[MAX_SUBPARTS]; uint8_t i; - if (fmap_locate_area_as_rdev_rw(region_name, &cse_rdev) < 0) { + if (cse_locate_area_as_rdev_rw(cse_bp_info, region_name, &cse_rdev)) { printk(BIOS_ERR, "cse_lite: Failed to locate %s in the FMAP\n", region_name); return false; } @@ -925,7 +952,7 @@ struct fw_version target_fw_ver, source_fw_ver; enum csme_failure_reason rv; size_t size; - static const char * const cse_regions[] = {"CSE_RO", "CSE_RW"}; + static const char * const cse_regions[] = {"RO", "RW"}; void *subpart_cbfs_rw = cbfs_map(name, &size); if (!subpart_cbfs_rw) { @@ -941,7 +968,7 @@ /* Trigger sub-partition update in CSE RO and CSE RW */ for (size_t bp = 0; bp < ARRAY_SIZE(cse_regions); bp++) { - if (!cse_sub_part_get_target_rdev(&target_rdev, cse_regions[bp], type)) { + if (!cse_sub_part_get_target_rdev(cse_bp_info, &target_rdev, cse_regions[bp], type)) { rv = CSE_LITE_SKU_SUB_PART_ACCESS_ERR; goto error_exit; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Hello build bot (Jenkins), Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62942 to look at the new patch set (#6). Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... drivers/intel/fsp2_0: Add provision to extract FSP Performance Data This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp from FPDT (Firmware Performance Data Table) and display right after FSP-S exits (from `fsp_silicon_init()` function), based on SoC user selects the required `DISPLAY_FSP_TIMESTAMP` config. The prerequisite to this implementation is to have FSP binary built with `PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate the FPDT HOB. BUG=b:216635831 TEST=Able to dump FSP performance data with DISPLAY_FSP_TIMESTAMP Kconfig selected and met the FSP prerequisites. +--------------------------------------------------+ |------ FSP Performance Timestamp Table Dump ------| +--------------------------------------------------+ |Perf-ID Timestamp(ms) String/GUID | +--------------------------------------------------+ 0 460253 SEC/52c05b14-0b98-496c-bc3b04b50211d680 50 460263 PEI/52c05b14-0b98-496c-bc3b04b50211d680 40 460274 PreMem/52c05b14-0b98-496c-bc3b04b50211d680 1 495803 9b3ada4f-ae56-4c24-8deaf03b7558ae50 2 508959 9b3ada4f-ae56-4c24-8deaf03b7558ae50 1 515253 6141e486-7543-4f1a-a579ff532ed78e75 2 525453 6141e486-7543-4f1a-a579ff532ed78e75 1 532059 baeb5bee-5b33-480a-8ab7b29c85e7ceab 2 546806 baeb5bee-5b33-480a-8ab7b29c85e7ceab 1 553302 1b04374d-fa9c-420f-ac62fee6d45e8443 2 563859 1b04374d-fa9c-420f-ac62fee6d45e8443 1 569955 88c17e54-ebfe-4531-a992581029f58126 2 575753 88c17e54-ebfe-4531-a992581029f58126 1 582099 a8499e65-a6f6-48b0-96db45c266030d83 50f0 599599 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 50f1 716649 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 2 728507 a8499e65-a6f6-48b0-96db45c266030d83 1 734755 9e1cc850-6731-4848-87526673c7005eee .... Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fsp_timestamp.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c 5 files changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62942/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/62942/comment/b16b4c8a_f892b84c PS5, Line 360: `PcdFspPerformanceEnable` set to `TRUE`. > Apparently it seems like we don't store any of the timestamps in coreboot, just printing out them. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:42:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Docs/project_ideas: Implement the ARM BBR spec in coreboot
by build bot (Jenkins) (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Felix Singer, Angel Pons, Julius Werner, Arthur Heymans, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63034 ) Change subject: Docs/project_ideas: Implement the ARM BBR spec in coreboot ...................................................................... Patch Set 4: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:38:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/brya/var/kano: adjust I2C3 speed"
by David Wu (Code Review) 29 Mar '22

29 Mar '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63168 ) Change subject: Revert "mb/google/brya/var/kano: adjust I2C3 speed" ...................................................................... Revert "mb/google/brya/var/kano: adjust I2C3 speed" This reverts commit 65aaccda5910e9c74aaa2a44ea84119d9476c902. Reason: Measure DVT I2C3 speed is 397KHz after revert this CL. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/63168/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 41c3cf2..5d7e30a 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -56,7 +56,7 @@ .data_hold_time_ns = 50, }, .i2c[3] = { - .speed = 390000, + .speed = I2C_SPEED_FAST, .rise_time_ns = 650, .fall_time_ns = 400, .data_hold_time_ns = 50, -- To view, visit https://review.coreboot.org/c/coreboot/+/63168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Gerrit-Change-Number: 63168 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Docs/project_ideas: Implement the ARM BBR spec in coreboot
by Arthur Heymans (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Felix Singer, Angel Pons, Julius Werner, Arthur Heymans, ron minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63034 ) Change subject: Docs/project_ideas: Implement the ARM BBR spec in coreboot ...................................................................... Patch Set 4: (1 comment) File Documentation/contributing/project_ideas.md: https://review.coreboot.org/c/coreboot/+/63034/comment/495defd0_74369fb8 PS1, Line 232: ## Make coreboot ARM (L)BBR compliant > > > It would be nice if this could emphasize a bit more that this is an _optional_ alternative confi […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:34:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Docs/project_ideas: Implement the ARM BBR spec in coreboot
by Arthur Heymans (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Felix Singer, Angel Pons, Julius Werner, Arthur Heymans, ron minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63034 ) Change subject: Docs/project_ideas: Implement the ARM BBR spec in coreboot ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63034/comment/075469e9_8e76b731 PS2, Line 7: Make coreboot ARM BBR compliant > > Please update accordingly as per Julius' comment […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Docs/project_ideas: Implement the ARM BBR spec in coreboot
by Arthur Heymans (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Arthur Heymans, Felix Singer, Angel Pons, Julius Werner, ron minnich. Arthur Heymans has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63034 ) Change subject: Docs/project_ideas: Implement the ARM BBR spec in coreboot ...................................................................... Docs/project_ideas: Implement the ARM BBR spec in coreboot Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/contributing/project_ideas.md 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/63034/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022