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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Michael Niewöhner, Andrey Petrov. Hello build bot (Jenkins), Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62942 to look at the new patch set (#7). Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... drivers/intel/fsp2_0: Add provision to extract FSP Performance Data This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp from FPDT (Firmware Performance Data Table) and display right after FSP-S exits (from `fsp_silicon_init()` function), based on SoC user selects the required `DISPLAY_FSP_TIMESTAMPS` config. The prerequisite to this implementation is to have FSP binary built with `PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate the FPDT HOB. BUG=b:216635831 TEST=Able to dump FSP performance data with DISPLAY_FSP_TIMESTAMPS Kconfig selected and met the FSP prerequisites. +--------------------------------------------------+ |------ FSP Performance Timestamp Table Dump ------| +--------------------------------------------------+ | Perf-ID Timestamp(ms) String/GUID | +--------------------------------------------------+ 0 460253 SEC/52c05b14-0b98-496c-bc3b04b50211d680 50 460263 PEI/52c05b14-0b98-496c-bc3b04b50211d680 40 460274 PreMem/52c05b14-0b98-496c-bc3b04b50211d680 1 495803 9b3ada4f-ae56-4c24-8deaf03b7558ae50 2 508959 9b3ada4f-ae56-4c24-8deaf03b7558ae50 1 515253 6141e486-7543-4f1a-a579ff532ed78e75 2 525453 6141e486-7543-4f1a-a579ff532ed78e75 1 532059 baeb5bee-5b33-480a-8ab7b29c85e7ceab 2 546806 baeb5bee-5b33-480a-8ab7b29c85e7ceab 1 553302 1b04374d-fa9c-420f-ac62fee6d45e8443 2 563859 1b04374d-fa9c-420f-ac62fee6d45e8443 1 569955 88c17e54-ebfe-4531-a992581029f58126 2 575753 88c17e54-ebfe-4531-a992581029f58126 1 582099 a8499e65-a6f6-48b0-96db45c266030d83 50f0 599599 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 50f1 716649 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 2 728507 a8499e65-a6f6-48b0-96db45c266030d83 1 734755 9e1cc850-6731-4848-87526673c7005eee .... Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fsp_timestamp.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c 5 files changed, 125 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62942/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Michael Niewöhner, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 6: (5 comments) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/62942/comment/fb6a622f_e81e23f5 PS6, Line 362: P > TIMESTAMPS? Ack https://review.coreboot.org/c/coreboot/+/62942/comment/eec655f1_61f9375b PS6, Line 363: bool > Shouldn't this be shown in menuconfig? Ack https://review.coreboot.org/c/coreboot/+/62942/comment/9e1d95a2_6b0a05ba PS6, Line 365: timestamp > timestamps? Ack https://review.coreboot.org/c/coreboot/+/62942/comment/697e4015_1d7a0978 PS6, Line 368: SoC users requires to compile and generate FSP binary with `PcdFspPerformanceEnable` : set to `TRUE`. > Mabye `To be able to use this, FSP has to be compiled with .... […] Ack File src/drivers/intel/fsp2_0/fsp_timestamp.c: https://review.coreboot.org/c/coreboot/+/62942/comment/22cf1a79_af7182db PS6, Line 82: |P > add a space, please Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 07:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Remove comment about OPWE
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63171 ) Change subject: ec/starlabs/merlin: Remove comment about OPWE ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/63171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a1310c779002dfb00d01a22437ea223bb406609 Gerrit-Change-Number: 63171 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 07:15:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Add GLKR variant
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62705 ) Change subject: ec/starlabs/merlin: Add GLKR variant ...................................................................... Patch Set 14: (1 comment) File src/ec/starlabs/merlin/variants/glkr/emem.asl: https://review.coreboot.org/c/coreboot/+/62705/comment/f115039d_3fe762ff PS14, Line 72: // Unicorn - doesn't actually exist > lolwut Lol - EC didn't know about OPWE, does now. I'll do a separate patch to remove them all -- To view, visit https://review.coreboot.org/c/coreboot/+/62705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81 Gerrit-Change-Number: 62705 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 07:12:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Add support for Nuvoton EC's
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62702 ) Change subject: ec/starlabs/merlin: Add support for Nuvoton EC's ...................................................................... Patch Set 13: (2 comments) File src/ec/starlabs/merlin/nuvoton.c: https://review.coreboot.org/c/coreboot/+/62702/comment/331c397e_1e55555d PS12, Line 132: EC_STARLABS_MAX_CHARGE > Please revise Kconfig dependencies Done https://review.coreboot.org/c/coreboot/+/62702/comment/38834b0b_a592c364 PS12, Line 154: EC_STARLABS_FAN > Please revise Kconfig dependencies Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95 Gerrit-Change-Number: 62702 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 07:09:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Rename ec.c to more specific ite.c
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62677 ) Change subject: ec/starlabs/merlin: Rename ec.c to more specific ite.c ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62677/comment/3ca8872f_88e13ee8 PS9, Line 7: ec/starlabs/merlin: Make ITE files dependent on Kconfig > Hmmm, this change merely renames a file. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 Gerrit-Change-Number: 62677 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 07:09:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Rename ec.c to more specific ite.c
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Sean Rhodes, Paul Menzel, Angel Pons. Hello build bot (Jenkins), Angel Pons, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62677 to look at the new patch set (#10). Change subject: ec/starlabs/merlin: Rename ec.c to more specific ite.c ...................................................................... ec/starlabs/merlin: Rename ec.c to more specific ite.c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 --- M src/ec/starlabs/merlin/Makefile.inc R src/ec/starlabs/merlin/ite.c 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/62677/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 Gerrit-Change-Number: 62677 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by build bot (Jenkins) (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Kane Chen. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63169 ) Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... Patch Set 1: (6 comments) File src/soc/intel/common/block/cse/cse_lite.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144923): https://review.coreboot.org/c/coreboot/+/63169/comment/87df2858_29045791 PS1, Line 782: static bool cse_locate_area_as_rdev_rw(const struct cse_bp_info *cse_bp_info, const char *region_name, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144923): https://review.coreboot.org/c/coreboot/+/63169/comment/b928a3ca_8f2c9af6 PS1, Line 783: struct region_device *cse_rdev) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144923): https://review.coreboot.org/c/coreboot/+/63169/comment/e9052183_e975bf8a PS1, Line 783: struct region_device *cse_rdev) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144923): https://review.coreboot.org/c/coreboot/+/63169/comment/8b3f7689_31798fa2 PS1, Line 803: printk(BIOS_DEBUG, "cse_lite: CSE %s partition: offset = 0x%x, size = 0x%x\n", region_name, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144923): https://review.coreboot.org/c/coreboot/+/63169/comment/b7217d90_bf44b7d8 PS1, Line 810: struct region_device *target_rdev, const char *region_name, enum bpdt_entry_type type) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144923): https://review.coreboot.org/c/coreboot/+/63169/comment/3346123f_2c3ba4c5 PS1, Line 971: if (!cse_sub_part_get_target_rdev(cse_bp_info, &target_rdev, cse_regions[bp], type)) { line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 07:06:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: move gpmr api to gpmr driver
by Wonkyu Kim (Code Review) 29 Mar '22

29 Mar '22

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63170 ) Change subject: intel/common/block: move gpmr api to gpmr driver ...................................................................... intel/common/block: move gpmr api to gpmr driver As gpmr api is not DMI specific, move api to gpmr driver Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b --- D src/soc/intel/common/block/dmi/Kconfig D src/soc/intel/common/block/dmi/Makefile.inc D src/soc/intel/common/block/dmi/dmi.c M src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/gpmr/Makefile.inc A src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/dmi.h A src/soc/intel/common/block/include/intelblocks/gpmr.h 8 files changed, 84 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/63170/1 diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/dmi/Kconfig deleted file mode 100644 index 2cc4646..0000000 --- a/src/soc/intel/common/block/dmi/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_DMI - bool - select SOC_INTEL_COMMON_BLOCK_PCR - help - Intel Processor common DMI support diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc deleted file mode 100644 index 7d013c9..0000000 --- a/src/soc/intel/common/block/dmi/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) - -bootblock-y += dmi.c -romstage-y += dmi.c -ramstage-y += dmi.c - -endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/dmi/dmi.c deleted file mode 100644 index 1a3a602..0000000 --- a/src/soc/intel/common/block/dmi/dmi.c +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <intelblocks/dmi.h> -#include <intelblocks/pcr.h> -#include <soc/pcr_ids.h> - -#define MAX_GPMR_REGS 3 - -#define GPMR_OFFSET(x) (0x277c + (x) * 8) -#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 -#define DMI_PCR_GPMR_BASE_SHIFT 16 -#define DMI_PCR_GPMR_BASE_MASK 0xffff - -#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) -#define DMI_PCR_GPMR_EN BIT(31) - -/* GPMR Register read given offset */ -static uint32_t gpmr_read32(uint16_t offset) -{ - return pcr_read32(PID_DMI, offset); -} - -/* GPMR Register write given offset and val */ -static void gpmr_write32(uint16_t offset, uint32_t val) -{ - return pcr_write32(PID_DMI, offset, val); -} - -/* Check for available free gpmr */ -static int get_available_gpmr(void) -{ - int i; - uint32_t val; - - for (i = 0; i < MAX_GPMR_REGS; i++) { - val = gpmr_read32(GPMR_DID_OFFSET(i)); - if (!(val & DMI_PCR_GPMR_EN)) - return i; - } - printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); - return CB_ERR; -} - -/* Configure GPMR for the given base and size of extended BIOS Region */ -enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) -{ - int gpmr_num; - uint32_t limit; - - if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { - printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); - return CB_ERR; - } - - limit = base + (size - 1); - - if (limit < base) { - printk(BIOS_ERR, "Invalid limit: limit cannot be less than base!\n"); - return CB_ERR; - } - - if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { - printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); - return CB_ERR; - } - - /* Get available free GPMR */ - gpmr_num = get_available_gpmr(); - if (gpmr_num == CB_ERR) - return CB_ERR; - - /* Program Range for the given decode window */ - gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | - ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); - - /* Program source decode enable bit and the Destination ID */ - gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); - - return CB_SUCCESS; -} diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 7be71a2..f0c288c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -10,7 +10,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> -#include <intelblocks/dmi.h> +#include <intelblocks/gpmr.h> #include <intelblocks/fast_spi.h> #include <lib.h> #include <soc/pci_devs.h> @@ -330,7 +330,7 @@ #endif /* Configure Source decode for Extended BIOS Region */ - if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, + if (enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_psf_destination_id()) == CB_ERR) return; diff --git a/src/soc/intel/common/block/gpmr/Makefile.inc b/src/soc/intel/common/block/gpmr/Makefile.inc new file mode 100644 index 0000000..20cf7b0 --- /dev/null +++ b/src/soc/intel/common/block/gpmr/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpmr.c +romstage-y += gpmr.c +ramstage-y += gpmr.c + diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c new file mode 100644 index 0000000..6a8126a --- /dev/null +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/dmi.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +#define MAX_GPMR_REGS 3 + +#define GPMR_LIMIT_MASK 0xffff0000 +#define GPMR_BASE_SHIFT 16 +#define GPMR_BASE_MASK 0xffff +#define GPMR_EN BIT(31) + +/* Check for available free gpmr */ +static int get_available_gpmr(void) +{ + int i; + uint32_t val; + + for (i = 0; i < MAX_GPMR_REGS; i++) { + val = pcr_read32(PID_DMI, PCR_GPMR_OFFSET(i)); + if (!(val & GPMR_EN)) + return i; + } + printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); + return CB_ERR; +} + +/* Configure GPMR for the given base and size of extended BIOS Region */ +enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) +{ + int gpmr_num; + uint32_t limit; + + if (base & ~(GPMR_BASE_MASK << GPMR_BASE_SHIFT)) { + printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); + return CB_ERR; + } + + limit = base + (size - 1); + + if (limit < base) { + printk(BIOS_ERR, "Invalid limit: limit cannot be less than base!\n"); + return CB_ERR; + } + + if ((limit & ~GPMR_LIMIT_MASK) != 0xffff) { + printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); + return CB_ERR; + } + + /* Get available free GPMR */ + gpmr_num = get_available_gpmr(); + if (gpmr_num == CB_ERR) + return CB_ERR; + + /* Program Range for the given decode window */ + pcr_write32(PID_DMI, PCR_GPMR_OFFSET(gpmr_num), (limit & GPMR_LIMIT_MASK) | + ((base >> GPMR_BASE_SHIFT) & GPMR_BASE_MASK)); + + /* Program source decode enable bit and the Destination ID */ + pcr_write32(PID_DMI, PCR_GPMR_DID_OFFSET(gpmr_num), dest_id | GPMR_EN); + + return CB_SUCCESS; +} diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index 8b12602..3f56b93 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -11,10 +11,7 @@ #define PCR_DMI_GCS 0x274C #define PCR_DMI_GCS_BILD (1 << 0) -/* - * Takes base, size and destination ID and configures the GPMR - * for accessing the region. - */ -enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); +#define PCR_GPMR_OFFSET(x) (0x277c + (x) * 8) +#define PCR_GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) #endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpmr.h b/src/soc/intel/common/block/include/intelblocks/gpmr.h new file mode 100644 index 0000000..a1d0fc3 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpmr.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GPMR_H +#define SOC_INTEL_COMMON_BLOCK_GPMR_H + +#include <types.h> + +enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_GPMR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Michael Niewöhner (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 6: (4 comments) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/62942/comment/ad4e32b6_5e7070a8 PS6, Line 362: P TIMESTAMPS? https://review.coreboot.org/c/coreboot/+/62942/comment/54e65c7e_545fe26a PS6, Line 363: bool Shouldn't this be shown in menuconfig? https://review.coreboot.org/c/coreboot/+/62942/comment/d41e9246_af688af0 PS6, Line 365: timestamp timestamps? https://review.coreboot.org/c/coreboot/+/62942/comment/53dd9dc1_2d2b3167 PS6, Line 368: SoC users requires to compile and generate FSP binary with `PcdFspPerformanceEnable` : set to `TRUE`. Mabye `To be able to use this, FSP has to be compiled with ....`? -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:58:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022