coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by John Zhao (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/block/include/intelblocks/cfg.h: https://review.coreboot.org/c/coreboot/+/62723/comment/49bb025e_de071591 PS13, Line 30: struct soc_tcss_ops tcss_ops; > IIUC, sconfig did that when build time :p You can check the statics. […] Probing the static.c and it shows elements assigned in the platform config struct. It seems nothing impacting the tcss_ops in the common_soc_config. -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 13 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:22:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
by Joey Peng (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62954 ) Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo ...................................................................... Patch Set 10: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62954/comment/b62b4f6c_003cdfeb PS9, Line 7: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL > Mention *tarlo* somewhere? Done https://review.coreboot.org/c/coreboot/+/62954/comment/f1ba96f4_efeb8067 PS9, Line 9: Add thermal table settings for tarlo which shares the same fw with taeko > Where is that documented, that *tarlo* and *taeko* are the same? Hi Paul, You can see https://partnerissuetracker.corp.google.com/issues/213982565#comment2 for more details. Thanks! File src/mainboard/google/brya/variants/taeko/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62954/comment/9c2b31b7_f3b73b30 PS9, Line 245: alias dptf_policy > Since this is unused, I'd also remove it in this CL so it doesn't get confusing Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 10 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 06:11:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
by Joey Peng (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: YH Lin, Joey Peng. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62954 to look at the new patch set (#10). Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo ...................................................................... mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo Add thermal table settings for tarlo which shares the same fw with taeko BUG=b:215033683 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62954/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 10 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63167 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG ...................................................................... soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG This patch binds all FSP-M and FSP-S UPDs required for serial redirection with `HAVE_FSP_DEBUG` config to allow coreboot to choose when to enable FSP debug output redirection to serial port. For example: PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S SerialDebugMrcLevel => For controllig MRC debug level. With this change FSP debug output will only be enabled when the user selects `HAVE_FSP_DEBUG` from site-local config with coreboot serial image. BUG=b:225544587 TEST=Able to build and boot brya. Also, the FSP debug log is exactly the same before and with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63167/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Gerrit-Change-Number: 63167 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG
by build bot (Jenkins) (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63167 ) Change subject: soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144917): https://review.coreboot.org/c/coreboot/+/63167/comment/0e4359e0_e2fae725 PS1, Line 377: else { else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/63167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Gerrit-Change-Number: 63167 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 05:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63167 ) Change subject: soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG ...................................................................... soc/intel/alderlake: Disable FSP debug output if !HAVE_FSP_DEBUG This patch binds all FSP-M and FSP-S UPDs required for serial redirection with `HAVE_FSP_DEBUG` config to allow coreboot to choose when to enable FSP debug output redirection to serial port. With this change FSP debug output will only be enabled when the user selects `HAVE_FSP_DEBUG` from site-local config with coreboot serial image. BUG=b:225544587 TEST=Able to build and boot brya. Also, the FSP debug log is exactly the same before and with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 22 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63167/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd2c0be..bd2331f 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -510,8 +510,11 @@ static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) - s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { + if (CONFIG(CONSOLE_SERIAL) && CONFIG(HAVE_FSP_DEBUG)) + s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + } /* PCH UART selection for FSP Debug */ s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2e76cd7..d1df88a 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -324,9 +324,6 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - /* Set MRC debug level */ - m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level(); - /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; @@ -367,10 +364,23 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) - arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) - fsp_debug_event_handler); - + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { + if (CONFIG(CONSOLE_SERIAL) && CONFIG(HAVE_FSP_DEBUG)) { + enum fsp_log_level log_level = fsp_map_console_log_level(); + arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + /* Set Serial debug message level */ + m_cfg->PcdSerialDebugLevel = log_level; + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = log_level; + } + else { + /* Disable Serial debug message */ + m_cfg->PcdSerialDebugLevel = 0; + /* Disable MRC debug message */ + m_cfg->SerialDebugMrcLevel = 0; + } + } config = config_of_soc(); soc_memory_init_params(m_cfg, config); -- To view, visit https://review.coreboot.org/c/coreboot/+/63167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Gerrit-Change-Number: 63167 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
by Subrata Banik (Code Review) 29 Mar '22

29 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63166 ) Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection ...................................................................... drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection coreboot has implemented native FSP debug handler with commit hash 3ba6f8cdf (drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler). However, coreboot still can't control when to redirect FSP debug output to the serial console, i.e., at present, integrating a FSP debug binary is enough to redirect FSP debug output to serial port, irrespective of whether coreboot user really wish to see FSP debug log with all the coreboot serial image. coreboot needs additional mechanism to control FSP debug binary to redirect debug messages over serial port. This patch introduces an config `HAVE_FSP_DEBUG` to control the FSP debug output, user to select this config from site-local config file incase like to override the default settings. There could be scenarios as below: Scenario 1: Non-serial coreboot image integrated with the FSP debug binaries, is capable of redirecting to the serial console, but coreboot decides to override the config as below to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_HAVE_FSP_DEBUG is not set Scenario 2: For coreboot serial image with FSP debug binaries integrated but coreboot decides to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_HAVE_FSP_DEBUG is not set CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 Scenario 3: The final image could be a coreboot serial image with FSP serial redirection enabled to output to the serial port. CONFIG_HAVE_FSP_DEBUG=y CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 BUG=b:227151510 TEST=Able to build and boot Redrix with all scenarios between #1- #3, and able to meet the expectation as mentioned above. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63166/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 0823aa3..45467f8 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -359,4 +359,16 @@ This option allows to create `Debug Event Handler` to print FSP debug messages to output device using coreboot native implementation. +config HAVE_FSP_DEBUG + bool "Have FSP debug binaries to get the console output" + default y + depends on FSP_USES_CB_DEBUG_EVENT_HANDLER + help + Send FSP debug output to the serial port. + + The config option is selected based on your FSP configuration i.e., debug or + release. Select this option from site-local to print FSP serial messages using + coreboot native serial debug driver when coreboot has integrated the debug FSP + binaries. + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 Gerrit-Change-Number: 63166 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: *.h: Fix up typos in guarding
by Jacob Garber (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Arthur Heymans, Anjaneya "Reddy" Chagam, Philipp Hug, Jonathan Zhang, Johnny Lin, Christian Walter, ron minnich, Tim Chu. Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63067 ) Change subject: *.h: Fix up typos in guarding ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I wonder if we should start using `#pragma once` to avoid these problems. -- To view, visit https://review.coreboot.org/c/coreboot/+/63067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1 Gerrit-Change-Number: 63067 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 05:52:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Kconfig SOC_INTEL_CSE_SET_EOP
by John Zhao (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, EricR Lai. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63159 ) Change subject: soc/intel/common: Add Kconfig SOC_INTEL_CSE_SET_EOP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > Yes, while rebasing for platform (which does not select this Kconfig SOC_INTEL_CSE_EOP) build, it […] I am working on platform other than MTL at early stage. If selecting SOC_INTEL_CS_EOP, do_send_end_of_post causes reboot. TBD for root cause. static void cse_final_ready_to_boot(void) { if (CONFIG(SOC_INTEL_CSE_SET_EOP)) cse_send_end_of_post(); cse_control_global_reset_lock(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { cse_set_to_d0i3(); heci1_disable(); } } Along with DISABLE_HECI1_AT_PRE_BOOT for heci1_disable(), it would be proper to add this CONFIG(SOC_INTEL_CSE_SET_EOP) for cse_send_end_of_post(). -- To view, visit https://review.coreboot.org/c/coreboot/+/63159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib52404d9ad4c01a460e4cfef331c529d2a53337a Gerrit-Change-Number: 63159 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 05:45:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Kangheui Won (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/62942/comment/a2e1511a_40b8dab5 PS5, Line 360: `PcdFspPerformanceEnable` set to `TRUE`. Apparently it seems like we don't store any of the timestamps in coreboot, just printing out them. In that case I think Kconfig name and description can be updated to state it more clear, wdyt? -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 05:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022