coreboot-gerrit March 2022

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Change in coreboot[master]: mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63164 ) Change subject: mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR ...................................................................... mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. TEST=Build the coreboot for adlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/63164/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 0d32746..20c37a0 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -1,6 +1,5 @@ config BOARD_INTEL_ADLRVP_COMMON def_bool n - select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID -- To view, visit https://review.coreboot.org/c/coreboot/+/63164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 Gerrit-Change-Number: 63164 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"
by Yu-Ping Wu (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63109 ) Change subject: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO" ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Gerrit-Change-Number: 63109 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 04:24:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62987 to look at the new patch set (#8). Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... soc/intel/alderlake: Log CSE RO write protection info for ADL The patch logs CSE RO's write protection information for Alder Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 --- M src/soc/intel/alderlake/me.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62987/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/62987/comment/afff0016_4388d191 PS7, Line 111: die > We will see the issue (mfg mode disabled but WP for CSE RO is not enabled) in the factory itself. […] Like EOM status, let's log only the status of WP status for CSE RO. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 03:30:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/62987/comment/43236357_26779a09 PS7, Line 111: die > Sorry I mean this, here, is it really worth halting boot here because of this? We will see the issue (mfg mode disabled but WP for CSE RO is not enabled) in the factory itself. If all goes well at factory, we will not see the buggy configuration in the shipping systems. Since, GPR0 protection can't be edited in the shipping system as this information is part of Descriptor Region. Adding the condition, it get caught in the factory itself. We can remove the halt, but we should have a factory test case ( or FAFT Test) that should report failure when the test is run. I check internally to extend EOM FAFT test case to cover CSE RO WP status. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 03:22:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Ensure PERST# deassertion time follows the spec
by Jianjun Wang (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Ensure PERST# deassertion time follows the spec ...................................................................... Patch Set 15: (2 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/7d581f38_5b88c09e PS14, Line 252: pre-initialize is not found, assert PERST# and sleep 100ms to met the delay requirement > early init data not found; sleeping 100ms Done https://review.coreboot.org/c/coreboot/+/62933/comment/f0d3146b_0a0e7036 PS14, Line 257: PERST# assert time %lld us is not enough for link up, sleep %lld us to met the 100ms delay requirement > Need an extra %lld us delay to meet PERST# deassertion requirement Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 03:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Ensure PERST# deassertion time follows the spec
by Jianjun Wang (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Angel Pons, Jianjun Wang. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62933 to look at the new patch set (#15). Change subject: soc/mediatek: Ensure PERST# deassertion time follows the spec ...................................................................... soc/mediatek: Ensure PERST# deassertion time follows the spec According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 --- M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/pcie.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/62933/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/acpi/acpigen_usb.c: Fix False Memory leak error
by vaibhav (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel. vaibhav has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62968 ) Change subject: src/acpi/acpigen_usb.c: Fix False Memory leak error ...................................................................... Patch Set 2: (1 comment) File src/acpi/acpigen_usb.c: https://review.coreboot.org/c/coreboot/+/62968/comment/024ccdc3_0f3ad4cd PS1, Line 89: free(fresh); > Done Found a way to get scan-build ignore this false error -- To view, visit https://review.coreboot.org/c/coreboot/+/62968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed611bd0b9c1da3678386bff33bca3eac0311b4 Gerrit-Change-Number: 62968 Gerrit-PatchSet: 2 Gerrit-Owner: vaibhav <vrockz747(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 02:36:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: vaibhav <vrockz747(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Ensure PERST# deassertion time follows the spec
by Yu-Ping Wu (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Ensure PERST# deassertion time follows the spec ...................................................................... Patch Set 14: (2 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/0d537934_c8547393 PS14, Line 252: pre-initialize is not found, assert PERST# and sleep 100ms to met the delay requirement early init data not found; sleeping 100ms https://review.coreboot.org/c/coreboot/+/62933/comment/7343e776_e481fae8 PS14, Line 257: PERST# assert time %lld us is not enough for link up, sleep %lld us to met the 100ms delay requirement Need an extra %lld us delay to meet PERST# deassertion requirement -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 02:35:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi/acpigen_usb.c: Fix False Memory leak error
by vaibhav (Code Review) 29 Mar '22

29 Mar '22

Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62968 to look at the new patch set (#2). Change subject: src/acpi/acpigen_usb.c: Fix False Memory leak error ...................................................................... src/acpi/acpigen_usb.c: Fix False Memory leak error Fix False Memory leak error detected by scan-build for: https://coreboot.org/scan-build/EMULATION_QEMU_X86_I440FX-scanbuild/ Signed-off-by: Vaibhav Sethia <vrockz747(a)gmail.com> Change-Id: Ifed611bd0b9c1da3678386bff33bca3eac0311b4 --- M src/acpi/acpigen_usb.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/62968/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed611bd0b9c1da3678386bff33bca3eac0311b4 Gerrit-Change-Number: 62968 Gerrit-PatchSet: 2 Gerrit-Owner: vaibhav <vrockz747(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022