coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: mb/google/nissa/var/nivviks: Move WWAN power on sequence forward
by Kangheui Won (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Tim Wawrzynczak, Eric Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63129 ) Change subject: mb/google/nissa/var/nivviks: Move WWAN power on sequence forward ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/… [View More]

1 0

Change in coreboot[master]: drivers/tpm: Force enable long IRQ pulses for Ti50 versions under 0.15.
by Kangheui Won (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Reka Norman. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63160 ) Change subject: drivers/tpm: Force enable long IRQ pulses for Ti50 versions under 0.15. ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/… [View More]

1 0

Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by John Zhao (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/block/include/intelblocks/cfg.h: https://review.coreboot.org/c/coreboot/… [View More]+/62723/comment/7d1c69b3_592cde45 PS13, Line 30: struct soc_tcss_ops tcss_ops; > Actually I'm not sure if this is the right place; this config structure can be filled in by devicetr […] Sorry, not sure what you meant to fill this tcss_ops struct, to platform specific struct along with chipset.cb/devicetree.cb? It seems devicetree usually sets the platform specific property. The tcss ops would need to be placed in the common_soc_conifg struct since it is actually referred by both of common block usb4 and relevant platforms like ADL/TGL. -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 13 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 01:30:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment [View Less]

1 0

Change in coreboot[master]: mb/google/brya/variants/crota: Add memory config for crota
by Terry Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Tim Wawrzynczak, Felix Held. Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63137 ) Change subject: mb/google/brya/variants/crota: Add memory config for crota ...................................................................... Patch Set 3: (5 comments) File src/mainboard/google/brya/variants/crota/memory.c: https://review.coreboot.org/c/coreboot/+/63137/comment/aa697402_dd159765 PS2, Line 74: __weak > … [View More]remove this Done. https://review.coreboot.org/c/coreboot/+/63137/comment/e98a3ef7_9f558c1a PS2, Line 79: __weak > remove this Done. https://review.coreboot.org/c/coreboot/+/63137/comment/04c16180_21afd84c PS2, Line 98: __weak > remove this Done. https://review.coreboot.org/c/coreboot/+/63137/comment/94d92835_06a053c5 PS2, Line 104: __weak > remove this Done. https://review.coreboot.org/c/coreboot/+/63137/comment/0c80d425_c6fdc107 PS2, Line 104: void __weak variant_get_spd_info(struct mem_spd *spd_info) : { : spd_info->topo = MEM_TOPO_MEMORY_DOWN; : spd_info->cbfs_index = variant_memory_sku(); : } > I don't think this override is required? Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/63137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Gerrit-Change-Number: 63137 Gerrit-PatchSet: 3 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Jesper Lin <jesper_lin(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Mar 2022 01:26:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment [View Less]

1 0

Change in coreboot[master]: mb/google/brya/variants/crota: init overridetree for crota
by Terry Chen (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, YH Lin. Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63022 ) Change subject: mb/google/brya/variants/crota: init overridetree for crota ...................................................................... Patch Set 9: (2 comments) File src/mainboard/google/brya/variants/crota/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63022/comment/… [View More]6d119aab_71a22113 PS8, Line 68: register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2_C4 : register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2_C6 : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port : register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_C8 > nit: use all tabs for indentation please (there are spaces at the beginning of these lines) Done. https://review.coreboot.org/c/coreboot/+/63022/comment/4b1d167c_027bcd5c PS8, Line 74: register "tcss_ports[1]" = "TCSS_PORT_EMPTY" > same here Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/63022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Gerrit-Change-Number: 63022 Gerrit-PatchSet: 9 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 01:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment [View Less]

1 0

Change in coreboot[master]: mb/amd/chausie/port_descriptors: update DDI descriptors
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nikolai Vyssotski, Fred Reitberger. Hello Nikolai Vyssotski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63163 to review the following change. Change subject: mb/amd/chausie/port_descriptors: update DDI descriptors ...................................................................... mb/amd/chausie/port_descriptors: update DDI descriptors Signed-off-by: Nikolai Vyssotski … [View More]<nikolai.vyssotski(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c --- M src/mainboard/amd/chausie/port_descriptors.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63163/1 diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 02e82b8..2609961 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -48,30 +48,30 @@ }; static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = { - { /* DDI0 - DP */ - .connector_type = DDI_DP, + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, .aux_index = DDI_AUX1, .hdp_index = DDI_HDP1 }, - { /* DDI1 - HDMI */ + { /* DDI1 - HDMI - TODO: add runtime HDMI/DP connector card detection */ .connector_type = DDI_HDMI, .aux_index = DDI_AUX2, .hdp_index = DDI_HDP2 }, - { /* DDI2 */ - .connector_type = DDI_UNUSED_TYPE, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP, .aux_index = DDI_AUX3, .hdp_index = DDI_HDP3, }, { /* DDI3 - DP (type C) */ .connector_type = DDI_DP, - .aux_index = DDI_AUX3, - .hdp_index = DDI_HDP3, - }, - { /* DDI4 - DP (type C) */ - .connector_type = DDI_DP, .aux_index = DDI_AUX4, .hdp_index = DDI_HDP4, + }, + { /* DDI4 - unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Gerrit-Change-Number: 63163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange [View Less]

1 0

Change in coreboot[master]: mb/amd/chausie/devicetree: update PCI root ports
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63162 ) Change subject: mb/amd/chausie/devicetree: update PCI root ports ...................................................................... mb/amd/chausie/devicetree: update PCI root ports Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the … [View More]

1 0

Change in coreboot[master]: mb/amd/chausie/port_descriptors: update DXIO descriptors
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Nikolai Vyssotski. Hello Nikolai Vyssotski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63161 to review the following change. Change subject: mb/amd/chausie/port_descriptors: update DXIO descriptors ...................................................................... mb/amd/chausie/port_descriptors: update DXIO descriptors Change the DXIO descriptors to match the default PCIe lane mapping on the … [View More]chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 --- M src/mainboard/amd/chausie/port_descriptors.c 1 file changed, 22 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/63161/1 diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 46afa77..02e82b8 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -5,91 +5,46 @@ #include <types.h> static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = { - { /* MXM */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 23, - .device_number = 1, - .function_number = 1, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SSD */ + { /* GBE*/ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 0, - .end_logical_lane = 1, + .end_logical_lane = 0, .device_number = 2, .function_number = 1, + .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5, - .gpio_group_id = GPIO_40, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + .link_aspm = 2, + .link_hotplug = 3, + .clk_req = CLK_REQ3, }, - { /* DT */ + { /* WIFI */ .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 4, - .end_logical_lane = 4, + .start_logical_lane = 1, + .end_logical_lane = 1, .device_number = 2, .function_number = 2, + .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ4_GFX, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* WWAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 5, - .end_logical_lane = 5, - .device_number = 2, - .function_number = 3, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* LAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 6, - .end_logical_lane = 6, - .device_number = 2, - .function_number = 4, - .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, .clk_req = CLK_REQ1, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, - { /* WLAN */ + { /* NVMe SSD */ .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 7, - .end_logical_lane = 7, - .device_number = 2, - .function_number = 5, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* TB */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 11, - .device_number = 2, - .function_number = 6, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SATA */ - .engine_type = SATA_ENGINE, - .port_present = true, .start_logical_lane = 2, .end_logical_lane = 3, - .channel_type = SATA_CHANNEL_LONG, - } + .device_number = 2, + .function_number = 3, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ0, + }, }; static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Gerrit-Change-Number: 63161 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange [View Less]

1 0

Change in coreboot[master]: src/mainboard/starlabs: Remove unused <option.h>
by Felix Singer (Code Review) 28 Mar '22

28 Mar '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60751 ) Change subject: src/mainboard/starlabs: Remove unused <option.h> ...................................................................... src/mainboard/starlabs: Remove unused <option.h> Found using: diff <(git grep -l '#include <option.h>' -- src/) <(git grep -l 'sanitize_cmos(\|get_uint_option(\|set_uint_option(\|get_uint_option(\|set_uint_option' -- src/) |grep "<" Change-… [View More]Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60751 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/starlabs/labtop/smbios.c M src/mainboard/starlabs/lite/mainboard.c M src/mainboard/starlabs/lite/smbios.c 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/starlabs/labtop/smbios.c b/src/mainboard/starlabs/labtop/smbios.c index b787986..22f3ad3 100644 --- a/src/mainboard/starlabs/labtop/smbios.c +++ b/src/mainboard/starlabs/labtop/smbios.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <ec/starlabs/merlin/ec.h> -#include <option.h> #include <smbios.h> #include <types.h> #include <uuid.h> diff --git a/src/mainboard/starlabs/lite/mainboard.c b/src/mainboard/starlabs/lite/mainboard.c index 60e65ee..0453709 100644 --- a/src/mainboard/starlabs/lite/mainboard.c +++ b/src/mainboard/starlabs/lite/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <soc/ramstage.h> -#include <option.h> #include <variants.h> static void init_mainboard(void *chip_info) diff --git a/src/mainboard/starlabs/lite/smbios.c b/src/mainboard/starlabs/lite/smbios.c index 7894ebb..3eaaf3a 100644 --- a/src/mainboard/starlabs/lite/smbios.c +++ b/src/mainboard/starlabs/lite/smbios.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <ec/starlabs/merlin/ec.h> -#include <option.h> #include <smbios.h> #include <types.h> #include <uuid.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3 Gerrit-Change-Number: 60751 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged [View Less]

1 0

Change in coreboot[master]: src/mainboard/starlabs: Remove unused <option.h>
by Felix Singer (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60751 ) Change subject: src/mainboard/starlabs: Remove unused <option.h> ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-… [View More]

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022