coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/mediatek: Add early_init for passing data across stages
by Paul Fagerburg (Code Review) 29 Mar '22

29 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add early_init for passing data across stages ...................................................................... soc/mediatek: Add early_init for passing data across stages Add support for "early_init_data" region, which can be used to store data initialized in an early stage (such as bootblock), and retrieve it in later stages (such as ramstage). TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/common/early_init.c A src/soc/mediatek/common/include/soc/early_init.h 2 files changed, 78 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/early_init.c b/src/soc/mediatek/common/early_init.c new file mode 100644 index 0000000..329663c --- /dev/null +++ b/src/soc/mediatek/common/early_init.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/early_init.h> +#include <stdlib.h> +#include <string.h> + +static struct early_init_data *find_early_init(void) +{ + assert(sizeof(struct early_init_data) <= REGION_SIZE(early_init_data)); + return (struct early_init_data *)_early_init_data; +} + +void early_init_clear(void) +{ + struct early_init_data *data = find_early_init(); + + if (!data) + return; + + memset(data, 0, sizeof(*data)); +} + +void early_init_save_time(enum early_init_type init_type) +{ + struct early_init_data *data = find_early_init(); + + if (!data) + return; + + timer_monotonic_get(&data->init_time[init_type]); +} + +uint64_t early_init_get_elapsed_time_us(enum early_init_type init_type) +{ + struct early_init_data *data = find_early_init(); + struct mono_time cur_time; + + if (!data) + return 0; + + memset(&cur_time, 0, sizeof(cur_time)); + + /* If early init data was never saved */ + if (!memcmp(&data->init_time[init_type], &cur_time, sizeof(cur_time))) + return 0; + + timer_monotonic_get(&cur_time); + + return mono_time_diff_microseconds(&data->init_time[init_type], + &cur_time); +} diff --git a/src/soc/mediatek/common/include/soc/early_init.h b/src/soc/mediatek/common/include/soc/early_init.h new file mode 100644 index 0000000..2811b0d --- /dev/null +++ b/src/soc/mediatek/common/include/soc/early_init.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_EARLY_INIT_H +#define SOC_MEDIATEK_EARLY_INIT_H + +#include <soc/symbols.h> +#include <stdint.h> +#include <symbols.h> +#include <timer.h> + +DECLARE_REGION(early_init_data); + +enum early_init_type { + EARLY_INIT_PCIE, + EARLY_INIT_MAX, +}; + +struct early_init_data { + struct mono_time init_time[EARLY_INIT_MAX]; +}; + +void early_init_clear(void); +void early_init_save_time(enum early_init_type init_type); +uint64_t early_init_get_elapsed_time_us(enum early_init_type init_type); + +#endif /* SOC_MEDIATEK_EARLY_INIT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: amdfwtool: Clear the whole byte of EFS_GEN
by Paul Fagerburg (Code Review) 29 Mar '22

29 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63138 ) Change subject: amdfwtool: Clear the whole byte of EFS_GEN ...................................................................... amdfwtool: Clear the whole byte of EFS_GEN Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f0fdd0a..0cfe307 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1785,6 +1785,7 @@ amd_romsig->imc_entry = 0; amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0; + amd_romsig->efs_gen.reserved = 0; if (soc_id != PLATFORM_UNKNOWN) { retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, -- To view, visit https://review.coreboot.org/c/coreboot/+/63138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Gerrit-Change-Number: 63138 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jett Rink (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Jes Klinke, Christian Walter, Julius Werner. Jett Rink has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... Patch Set 1: (1 comment) File src/drivers/spi/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/63158/comment/6f2fc3ec_80818290 PS1, Line 515: if (tpm_first_access_this_boot()) { : /* This is called for the side-effect of printing the firmware version : string */ : cr50_get_firmware_version(&ver); : } > tpm_first_access_this_boot() is a function which returns true in the first stage where this code run […] I am getting it now. I wasn't looking at enough code. I think the rename will help. Otherwise the code flow looks good -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 15:39:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jes Klinke <jbk(a)chromium.org> Comment-In-Reply-To: Jett Rink <jettrink(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Christian Walter, Julius Werner, Jett Rink. Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... Patch Set 1: (1 comment) File src/drivers/spi/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/63158/comment/ae3f23c2_306327af PS1, Line 515: if (tpm_first_access_this_boot()) { : /* This is called for the side-effect of printing the firmware version : string */ : cr50_get_firmware_version(&ver); : } > I think renaming to gsc when it applies to both is helpful. […] tpm_first_access_this_boot() is a function which returns true in the first stage where this code runs, and false in every subsequent stage. We want to call it in both cases in order to only print the Cr50/Ti50 version string once during boot. (And also in the Cr50 case such that the interrupt pulse length workaround runs only once, and as early as possible.) Let me work on renaming cr50_firmware_version. -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jett Rink <jettrink(a)google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 15:34:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jes Klinke <jbk(a)chromium.org> Comment-In-Reply-To: Jett Rink <jettrink(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add support to control CSE firmware update
by Sridhar Siricilla (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Rizwan Qureshi, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62715 ) Change subject: soc/intel/common: Add support to control CSE firmware update ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/62715/comment/4dbb30e7_f5ad915f PS3, Line 34: fmap_locate_area_as_rdev_rw > Does fmap_locate_area_as_rdev work too? I'm not sure if this will attempt to use memory mapped mediu […] In this case, fmap_locate_area_as_rdev() can work. -- To view, visit https://review.coreboot.org/c/coreboot/+/62715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba Gerrit-Change-Number: 62715 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 15:18:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... soc/amd/common/block/lpc: Add support to not clear port80 enable SMU locks up sometimes if the port80 enable bit is cleared in the ESPI Decode register. Add a config to choose between clearing the entire ESPI Decode Register vs retaining the port80 enable bit. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 12 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index 6419269..125f8b3 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -42,3 +42,11 @@ help Select this option if mainboard uses eSPI instead of LPC (if supported by platform). + +config SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN + bool + depends on SOC_AMD_COMMON_BLOCK_USE_ESPI + help + SMU will lock up at times if the port80h enable bit is cleared. Select + this option to retain the port80 enable bit while clearing other enable + bits in the ESPI Decode register. diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c61c61f..68d51f5 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -139,7 +139,10 @@ unsigned int idx; /* First turn off all enable bits, then zero base, range, and size registers */ - espi_write16(ESPI_DECODE, 0); + if (CONFIG(SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN)) + espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); + else + espi_write16(ESPI_DECODE, 0); for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { espi_write16(espi_io_range_base_reg(idx), 0); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/variants/crota: init overridetree for crota
by Tim Wawrzynczak (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Terry Chen, Paul Menzel, Zhuohao Lee, YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63022 ) Change subject: mb/google/brya/variants/crota: init overridetree for crota ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Gerrit-Change-Number: 63022 Gerrit-PatchSet: 9 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 14:36:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: commonlib/bsd/helpers: Remove redundancy with libpayload defines
by Tim Wawrzynczak (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Jakub Czapiga, Julius Werner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62921 ) Change subject: commonlib/bsd/helpers: Remove redundancy with libpayload defines ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: > It should be ok. […] Gotcha, thanks for clarification -- To view, visit https://review.coreboot.org/c/coreboot/+/62921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Gerrit-Change-Number: 62921 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 14:34:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63116 ) Change subject: mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC ...................................................................... mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC Configure GPIO according to b:224107199 comment#15. - GPP_E19 from NF to NC. BUG=b:224107199 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/felwinter/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, but someone else must approve Derek Huang: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 26af4ab..bff8bb2 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -53,6 +53,8 @@ PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> NC */ PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Gerrit-Change-Number: 63116 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63114 ) Change subject: soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO ...................................................................... soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO The feature "USE_CBMEM_DRAM_INFO" is supported in MT8186. Therefore, we select this configuration to enable it. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de Reviewed-on: https://review.coreboot.org/c/coreboot/+/63114 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8186/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index 654baf2..61843e3 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -10,6 +10,7 @@ select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON select MEDIATEK_BLOB_FAST_INIT + select USE_CBMEM_DRAM_INFO if SOC_MEDIATEK_MT8186 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de Gerrit-Change-Number: 63114 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022