coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63109 ) Change subject: soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO" ...................................................................... soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO" The memory initialization reference code didn't support returning DRAM information in the old platforms, for example MT8192 and MT8195. So we have to add a new configuration USE_CBMEM_DRAM_INFO to make sure the common code will try to get DRAM information on new platforms supporting that. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/memory.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index cd3b2a2..2adb344 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -50,4 +50,10 @@ and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM to store logs of DFD. +config USE_CBMEM_DRAM_INFO + bool "Support filling dram information to cbmem" + help + The DRAM initialization will keep and return DRAM information (size, + geometry and other DDR info) so we can fill that into the CBMEM. + endif diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 0850d0f..ab1ccb5 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -134,6 +134,12 @@ struct mem_chip_info *mc; size_t size; + if (!CONFIG(USE_CBMEM_DRAM_INFO)) { + printk(BIOS_DEBUG, + "DRAM-K: CBMEM DRAM info is unsupported (USE_CBMEM_DRAM_INFO)\n"); + return; + } + size = sizeof(*mc) + sizeof(struct mem_chip_channel) * CHANNEL_MAX; mc = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, size); assert(mc); -- To view, visit https://review.coreboot.org/c/coreboot/+/63109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Gerrit-Change-Number: 63109 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Fix pmif setting for low power mode
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63089 ) Change subject: soc/mediatek/mt8186: Fix pmif setting for low power mode ...................................................................... soc/mediatek/mt8186: Fix pmif setting for low power mode The current pmif register setting for low power mode is incorrect, which is causing suspend failure. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode() to correct the setting. This implementation is based on chapter 3.7 in MT8186 Functional Specification. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Zhiyong Tao <zhiyong.tao(a)mediatek.com> Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/pmif.h M src/soc/mediatek/mt8186/mt6366.c A src/soc/mediatek/mt8186/pmif.c 5 files changed, 42 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 0d56f15..5d327e0 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -40,7 +40,7 @@ romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c -romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += ../common/auxadc.c @@ -64,7 +64,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/wdt.c wdt.c -ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c BL31_MAKEARGS += PLAT=mt8186 diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index c90e0cd..069e31d 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -30,6 +30,7 @@ PWRAP_BASE = IO_PHYS + 0x0000D000, DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000, DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000, + PMIF_BASE = IO_PHYS + 0x00015000, SYSTIMER_BASE = IO_PHYS + 0x00017000, I2C0_DMA_BASE = IO_PHYS + 0x00200100, I2C1_DMA_BASE = IO_PHYS + 0x00200200, diff --git a/src/soc/mediatek/mt8186/include/soc/pmif.h b/src/soc/mediatek/mt8186/include/soc/pmif.h new file mode 100644 index 0000000..0e1e1a2 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/pmif.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef __SOC_MEDIATEK_MT8186_PMIF_H__ +#define __SOC_MEDIATEK_MT8186_PMIF_H__ + +#include <soc/addressmap.h> +#include <types.h> + +void pmif_spmi_set_lp_mode(void); + +#endif /*__SOC_MEDIATEK_MT8186_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 30ae5e0..8dd2997 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -10,6 +10,7 @@ #include <delay.h> #include <soc/mt6366.h> #include <soc/pmic_wrap.h> +#include <soc/pmif.h> #include <soc/regulator.h> #include <timer.h> @@ -953,6 +954,7 @@ wk_sleep_voltage_by_ddr(); wk_power_down_seq(); mt6366_lp_setting(); + pmif_spmi_set_lp_mode(); while (!stopwatch_expired(&voltage_settled)) /* wait for voltages to settle */; diff --git a/src/soc/mediatek/mt8186/pmif.c b/src/soc/mediatek/mt8186/pmif.c new file mode 100644 index 0000000..b909609 --- /dev/null +++ b/src/soc/mediatek/mt8186/pmif.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#include <device/mmio.h> +#include <soc/pmif.h> + +#define SLEEP_PROT_CTRL 0x3F0 + +DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) + +void pmif_spmi_set_lp_mode(void) +{ + SET32_BITFIELDS((void *)(PMIF_BASE + SLEEP_PROT_CTRL), + SPM_SLEEP_REQ_SEL, 0, + SCP_SLEEP_REQ_SEL, 0); +} 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Gerrit-Change-Number: 63089 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: gpio: Update table as per coreboot guidelines
by Eric Lai (Code Review) 29 Mar '22

29 Mar '22

Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63126 ) Change subject: Documentation: gpio: Update table as per coreboot guidelines ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: the table is good now, but small problem. - turns to . -- To view, visit https://review.coreboot.org/c/coreboot/+/63126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce Gerrit-Change-Number: 63126 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 14:16:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: gpio: Update table as per coreboot guidelines
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63126 ) Change subject: Documentation: gpio: Update table as per coreboot guidelines ...................................................................... Documentation: gpio: Update table as per coreboot guidelines This patch fixes the table issue in markdown file introduced with commit 5338a16b (Documentation: gpio: Fix table). BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce Reviewed-on: https://review.coreboot.org/c/coreboot/+/63126 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M Documentation/getting_started/gpio.md 1 file changed, 55 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 5f30ea7..216ba5d 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -167,32 +167,61 @@ As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register supports four different types of GPIO reset as: -| PAD Reset Config | Platform Reset | GPP | GPD | -|-------------------------------------------------|----------------|-----|-----| -| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N | -| | Cold Reset | N | N | -| | S3/S4/S5 | N | N | -| | Global Reset | N | N | -| | Deep Sx | Y | N | -| | G3 | Y | N | -| 01 - Deep | Warm Reset | Y | Y | -| | Cold Reset | Y | Y | -| | S3/S4/S5 | N | N | -| | Global Reset | Y | Y | -| | Deep Sx | Y | Y | -| | G3 | Y | Y | -| 10 - Host Reset/PLTRST | Warm Reset | Y | Y | -| | Cold Reset | Y | Y | -| | S3/S4/S5 | Y | Y | -| | Global Reset | Y | Y | -| | Deep Sx | Y | Y | -| | G3 | Y | Y | -| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N | -| | Cold Reset | - | N | -| | S3/S4/S5 | - | N | -| | Global Reset | - | N | -| | Deep Sx | - | Y | -| | G3 | - | Y | +```eval_rst ++------------------------+----------------+-------------+-------------+ +| | | PAD Reset ? | ++ PAD Reset Config + Platform Reset +-------------+-------------+ +| | | GPP | GPD | ++========================+================+=============+=============+ +| | 00 - Power Good | Warm Reset | N | N | +| | (GPP: RSMRST, +----------------+-------------+-------------+ +| | GPD: DSW_PWROK) | Cold Reset | N | N | +| |----------------+-------------+-------------+ +| | S3/S4/S5 | N | N | +| +----------------+-------------+-------------+ +| | Global Reset | N | N | +| +----------------+-------------+-------------+ +| | Deep Sx | Y | N | +| +----------------+-------------+-------------+ +| | G3 | Y | Y | ++------------------------+----------------+-------------+-------------+ +| 01 - Deep | Warm Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Cold Reset | Y | Y | +| +----------------+-------------+-------------+ +| | S3/S4/S5 | N | N | +| +----------------+-------------+-------------+ +| | Global Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Deep Sx | Y | Y | +| +----------------+-------------+-------------+ +| | G3 | Y | Y | ++------------------------+----------------+-------------+-------------+ +| 10 - Host Reset/PLTRST | Warm Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Cold Reset | Y | Y | +| +----------------+-------------+-------------+ +| | S3/S4/S5 | Y | Y | +| +----------------+-------------+-------------+ +| | Global Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Deep Sx | Y | Y | +| +----------------+-------------+-------------+ +| | G3 | Y | Y | ++------------------------+----------------+-------------+-------------+ +| | 11 - Resume Reset | Warm Reset | - | N | +| | (GPP: Reserved, +----------------+-------------+-------------+ +| | GPD: RSMRST) | Cold Reset | - | N | +| +----------------+-------------+-------------+ +| | S3/S4/S5 | - | N | +| +----------------+-------------+-------------+ +| | Global Reset | - | N | +| +----------------+-------------+-------------+ +| | Deep Sx | - | Y | +| +----------------+-------------+-------------+ +| | G3 | - | Y | ++------------------------+----------------+-------------+-------------+ +``` Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking specific register fields in the PAD configuration register. -- To view, visit https://review.coreboot.org/c/coreboot/+/63126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce Gerrit-Change-Number: 63126 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: support max98390 audio amp
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63083 ) Change subject: mb/google/cherry: support max98390 audio amp ...................................................................... mb/google/cherry: support max98390 audio amp The Cherry follower projects may choose Max98390 for audio output so we have to add a new config CHERRY_USE_MAX98390. Also, the 'dojo' device is the first one to use it. BUG=b:204391159 BRANCH=cherry TEST=emerge-cherry coreboot TEST=Verify beep function through CLI in depthcharge successfully Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/pll.c 5 files changed, 55 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index e45b259..51ad029 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -57,11 +57,18 @@ hex default 0x0 -config CHERRY_USE_RT1011 - bool - default n +choice + prompt "Speaker AMP for Cherry" + default CHERRY_USE_RT1019 if BOARD_GOOGLE_CHERRY || BOARD_GOOGLE_TOMATO + default CHERRY_USE_MAX98390 if BOARD_GOOGLE_DOJO +config CHERRY_USE_RT1011 + bool "RT1011" config CHERRY_USE_RT1019 - bool - default y + bool "RT1019" +config CHERRY_USE_MAX98390 + bool "MAX98390" + +endchoice + endif diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 13b673c..301a0bc 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -47,12 +47,18 @@ {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, }; + struct lb_gpio spk_gpios[] = { + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); if (CONFIG(CHERRY_USE_RT1019)) lb_add_gpios(gpios, rt1019_gpios, ARRAY_SIZE(rt1019_gpios)); else if (CONFIG(CHERRY_USE_RT1011)) lb_add_gpios(gpios, rt1011_gpios, ARRAY_SIZE(rt1011_gpios)); + else if (CONFIG(CHERRY_USE_MAX98390)) + lb_add_gpios(gpios, spk_gpios, ARRAY_SIZE(spk_gpios)); } int tis_plat_irq_status(void) diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 92d8ee1..3fb599b 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -92,6 +92,27 @@ return true; } +static void configure_i2s(void) +{ + /* Audio PWR */ + mtcmos_audio_power_on(); + mtcmos_protect_audio_bus(); + + /* SoC I2S */ + gpio_set_mode(GPIO(GPIO_02), PAD_GPIO_02_FUNC_TDMIN_LRCK); + gpio_set_mode(GPIO(GPIO_03), PAD_GPIO_03_FUNC_TDMIN_BCK); + gpio_set_mode(GPIO(I2SO2_D0), PAD_I2SO2_D0_FUNC_I2SO2_D0); +} + +static void configure_audio(void) +{ + if (CONFIG(CHERRY_USE_RT1011) || CONFIG(CHERRY_USE_MAX98390)) + mtk_i2c_bus_init(I2C2, I2C_SPEED_FAST); + + if (CONFIG(CHERRY_USE_MAX98390)) + configure_i2s(); +} + static void mainboard_init(struct device *dev) { if (display_init_required()) @@ -103,9 +124,7 @@ mtk_msdc_configure_sdcard(); setup_usb_host(); - /* for audio usage */ - if (CONFIG(CHERRY_USE_RT1011)) - mtk_i2c_bus_init(I2C2, I2C_SPEED_FAST); + configure_audio(); if (dpm_init()) printk(BIOS_ERR, "dpm init failed, DVFS may not work\n"); diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index f2714da..a5c4b0d 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -49,6 +49,7 @@ SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, SCP_CFG_BASE = IO_PHYS + 0x00700000, + SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index df4ae30..046008c 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -28,6 +28,14 @@ check_member(mt8195_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010); static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao = (void *)PERICFG_AO_BASE; +struct mt8195_scp_adsp_regs { + u32 reserved1[96]; + u32 audiodsp_ck_cg; /* 0x180 */ +}; +check_member(mt8195_scp_adsp_regs, audiodsp_ck_cg, 0x0180); +static struct mt8195_scp_adsp_regs *const mt8195_scp_adsp = + (void *)SCP_ADSP_CFG_BASE; + enum mux_id { TOP_AXI_SEL, TOP_SPM_SEL, @@ -760,6 +768,12 @@ /* turn off unused clock */ write32(&mt8195_pericfg_ao->peri_module_sw_cg_0_set, 0x10); + + /* scp_dsp for audio */ + clrbits32(&mt8195_scp_adsp->audiodsp_ck_cg, BIT(0)); + + /* audio 26M */ + setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(4)); } void mt_pll_raise_little_cpu_freq(u32 freq) -- To view, visit https://review.coreboot.org/c/coreboot/+/63083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Gerrit-Change-Number: 63083 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Trevor Wu <trevor.wu(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Felix Held (Code Review) 29 Mar '22

29 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62064 ) Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeff Daly <jeffd(a)silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c 31 files changed, 57 insertions(+), 173 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Jeff Daly: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 37c0b62..25d11d3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -104,6 +104,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h index b65b24d..98843d1 100644 --- a/src/soc/intel/alderlake/include/soc/pm.h +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -162,9 +162,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index d8308b4..f8b858f 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -133,20 +133,6 @@ write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 91d203e..9e48971 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -107,6 +107,7 @@ select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SOC_INTEL_NO_BOOTGUARD_MSR select SOUTHBRIDGE_INTEL_COMMON_SMBUS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3c0b1e7..1e6a927 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -242,7 +242,4 @@ /* STM Support */ uint16_t get_pmbase(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 79ece4b..fbb2345 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -237,17 +237,3 @@ reg32 |= SLEEP_AFTER_POWER_FAIL; write32p(gen_pmcon1, reg32); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON1); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON1), reg_val); -} diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9517cee..0a61381 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -105,6 +105,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 59b2ba0..d345e07 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a79d262..38a0ce7 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -127,20 +127,6 @@ write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index bb38204..fc65a08 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -178,6 +178,9 @@ */ void pmc_gpe_init(void); +/* Clear PMC GEN_PMCON_A register status bits */ +void pmc_clear_pmcon_sts(void); + /* Power Management Utility Functions. */ /* Returns PMC base address */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index fa1a990..effdc12 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -10,6 +10,12 @@ if SOC_INTEL_COMMON_BLOCK_PMC +config SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION + bool + help + Select this on platforms where the PMC register for PM configuration (i.e., + GEN_PMCON_A/B etc. are memory mapped). + config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index b6a2fc9..51b2aa6 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <intelblocks/acpi.h> #include <intelblocks/pmc.h> +#include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index da78d5c..a2e3e9e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -5,6 +5,7 @@ #include <assert.h> #include <bootmode.h> #include <device/mmio.h> +#include <device/pci.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <console/console.h> @@ -14,6 +15,7 @@ #include <intelblocks/tco.h> #include <option.h> #include <security/vboot/vboot_common.h> +#include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> #include <string.h> @@ -580,6 +582,44 @@ gpio_route_gpe(dw0, dw1, dw2); } +#if ENV_RAMSTAGE +static void pmc_clear_pmcon_sts_mmio(void) +{ + uint8_t *addr = pmc_mmio_regs(); + + clrbits32((addr + GEN_PMCON_A), MS4V); +} + +static void pmc_clear_pmcon_sts_pci(void) +{ + struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!dev) + return; + + pci_and_config32(dev, GEN_PMCON_A, ~MS4V); +} + +/* + * Clear PMC GEN_PMCON_A register status bits: + * SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit + */ +void pmc_clear_pmcon_sts(void) +{ + /* + * Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. + * Typically, there are two possible ways to perform GEN_PMCON_A register programming + * (like `pmc_clear_pmcon_sts()`) as: + * 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. + * 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. + */ + if (CONFIG(SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION)) + pmc_clear_pmcon_sts_mmio(); + else + pmc_clear_pmcon_sts_pci(); +} +#endif + void pmc_set_power_failure_state(const bool target_on) { const unsigned int state = get_uint_option("power_on_after_fail", diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index faf7f20..368fac8 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -48,7 +48,4 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index b861513..8d670c6 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -247,18 +247,3 @@ uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } void clear_pmc_status(void) { /* TODO */ } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index a1f7794..b2d322ca 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -58,6 +58,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6ebbbfa..6a86787 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 9bd431d..0109215 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index ae693a4..d884551 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -56,6 +56,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index ad2beff..05db830 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index f552a8c..b7829b2 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 48b735e..e0e0c7b 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index 11d6663..eea875b 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index d9ecb63..fb1aecd 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 51be0eb..f0ce146 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -189,7 +189,4 @@ /* STM Support */ uint16_t get_pmbase(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index ded44dc..fe26ebf 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -265,18 +265,3 @@ reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(dev, GEN_PMCON_B, reg8); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2b673cab..df5c167 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -80,6 +80,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index d62e8ad..cb0781a 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -162,9 +162,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index aee2b3b..e854385 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -132,20 +132,6 @@ write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index 63b15cd..b4d6df9 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -121,7 +121,4 @@ void pmc_lock_smi(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index 14c7da8..c63285c 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -179,18 +179,3 @@ reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Rename ec.c to more specific ite.c
by Angel Pons (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Sean Rhodes, Angel Pons. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62677 ) Change subject: ec/starlabs/merlin: Rename ec.c to more specific ite.c ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 Gerrit-Change-Number: 62677 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 13:47:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Add support for Nuvoton EC's
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62702 ) Change subject: ec/starlabs/merlin: Add support for Nuvoton EC's ...................................................................... Patch Set 14: (1 comment) File src/ec/starlabs/merlin/Kconfig: https://review.coreboot.org/c/coreboot/+/62702/comment/5f99f141_9b2c3cef PS13, Line 7: Interface to Nuvoton embedded controller > Also mention the EC firmware here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95 Gerrit-Change-Number: 62702 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 13:15:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Add support for Nuvoton EC's
by Sean Rhodes (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Sean Rhodes, Angel Pons. Hello build bot (Jenkins), Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62702 to look at the new patch set (#14). Change subject: ec/starlabs/merlin: Add support for Nuvoton EC's ...................................................................... ec/starlabs/merlin: Add support for Nuvoton EC's Support was created for the NPCE9m5x series, using version 1.1 of the datasheet. The specific model tested was the NPCE985P/G, on the StarLite Mk IV with version 1.00 of the EC firmware. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95 --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/Makefile.inc M src/ec/starlabs/merlin/ec.h A src/ec/starlabs/merlin/nuvoton.c 4 files changed, 322 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/62702/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/62702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95 Gerrit-Change-Number: 62702 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
by Paul Menzel (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Arthur Heymans, Lean Sheng Tan, Andrey Petrov. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63166 ) Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection ...................................................................... Patch Set 1: (5 comments) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/63166/comment/0c977b7a_27cdbc7f PS1, Line 362: HAVE_FSP_DEBUG Maybe: `FSP_ENABLE_SERIAL_DEBUG` https://review.coreboot.org/c/coreboot/+/63166/comment/eee53c04_16142594 PS1, Line 363: Have FSP debug binaries to get the console output Maybe: Output FSP debug messages on serial console https://review.coreboot.org/c/coreboot/+/63166/comment/2c8701ac_398428a1 PS1, Line 370: Select this option from site-local Why site-local? https://review.coreboot.org/c/coreboot/+/63166/comment/7e19130d_9b53b2a1 PS1, Line 371: serial debug Without “debug”? https://review.coreboot.org/c/coreboot/+/63166/comment/41d935b6_04b1dfa8 PS1, Line 372: binaries. What happens, when you have non-FSP debug builds? Is there an error, or just no messages are send to serial console? -- To view, visit https://review.coreboot.org/c/coreboot/+/63166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 Gerrit-Change-Number: 63166 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 13:05:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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