coreboot-gerrit March 2022

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Change in coreboot[master]: Revert "mb/google/brya/var/kano: adjust I2C3 speed"
by Tim Wawrzynczak (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: David Wu, Paul Menzel, Ren Kuo. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63168 ) Change subject: Revert "mb/google/brya/var/kano: adjust I2C3 speed" ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Gerrit-Change-Number: 63168 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 16:47:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: gpio: Update table as per coreboot guidelines
by Michael Niewöhner (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63126 ) Change subject: Documentation: gpio: Update table as per coreboot guidelines ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: > the table is good now, but small problem. - turns to . yeah :/ needs to be escaped: `\-` File Documentation/getting_started/gpio.md: https://review.coreboot.org/c/coreboot/+/63126/comment/e229582f_5a3e8c7c PS4, Line 179: | meh. I had missed this. should be a + -- To view, visit https://review.coreboot.org/c/coreboot/+/63126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce Gerrit-Change-Number: 63126 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 16:46:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add early_init for passing data across stages
by Paul Menzel (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add early_init for passing data across stages ...................................................................... Patch Set 12: (1 comment) File src/soc/mediatek/common/early_init.c: https://review.coreboot.org/c/coreboot/+/63019/comment/e727b2e6_1679c12c PS12, Line 34: uint64_t The signature of mono_time_diff_microseconds is long. Why not use the same? -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 16:42:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Tim Wawrzynczak (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/62987/comment/4b64e667_5b20ab31 PS7, Line 111: die > Like EOM status, let's log only the status of WP status for CSE RO. […] Thanks Sridhar, that seems much better to me! -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 29 Mar 2022 16:32:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: move gpmr api to gpmr driver
by Wonkyu Kim (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Wonkyu Kim. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63170 to look at the new patch set (#4). Change subject: intel/common/block: move gpmr api to gpmr driver ...................................................................... intel/common/block: move gpmr api to gpmr driver As gpmr api is not DMI specific, move api to gpmr driver Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b --- D src/soc/intel/common/block/dmi/Makefile.inc M src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/gpmr/Kconfig A src/soc/intel/common/block/gpmr/Makefile.inc R src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/dmi.h A src/soc/intel/common/block/include/intelblocks/gpmr.h M src/soc/intel/common/pch/Kconfig 8 files changed, 42 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/63170/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/common/block: move gpmr api to gpmr driver
by Wonkyu Kim (Code Review) 29 Mar '22

29 Mar '22

Attention is currently required from: Wonkyu Kim. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63170 to look at the new patch set (#3). Change subject: intel/common/block: move gpmr api to gpmr driver ...................................................................... intel/common/block: move gpmr api to gpmr driver As gpmr api is not DMI specific, move api to gpmr driver Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b --- D src/soc/intel/common/block/dmi/Makefile.inc D src/soc/intel/common/block/dmi/dmi.c M src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/gpmr/Kconfig A src/soc/intel/common/block/gpmr/Makefile.inc A src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/dmi.h A src/soc/intel/common/block/include/intelblocks/gpmr.h M src/soc/intel/common/pch/Kconfig 9 files changed, 99 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/63170/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO
by 9elements QA (Code Review) 29 Mar '22

29 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63114 ) Change subject: soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO ...................................................................... Patch Set 10: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/97698 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/97697 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/97696 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/97695 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/97694 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/97693 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/97692 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/97691 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/97690 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/97689 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/97688 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/97687 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de Gerrit-Change-Number: 63114 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 29 Mar 2022 15:49:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Ensure PERST# deassertion time follows the spec
by Paul Fagerburg (Code Review) 29 Mar '22

29 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Ensure PERST# deassertion time follows the spec ...................................................................... soc/mediatek: Ensure PERST# deassertion time follows the spec According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/pcie.c 2 files changed, 31 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c46b53f..3a75f6b 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -11,6 +11,7 @@ #include <delay.h> #include <lib.h> #include <soc/addressmap.h> +#include <soc/early_init.h> #include <soc/pcie.h> #include <soc/pcie_common.h> #include <soc/soc_chip.h> @@ -214,6 +215,7 @@ const mtk_soc_config_t *config = config_of(dev); const struct mtk_pcie_config *conf = &config->pcie_config; const char *ltssm_state; + uint64_t perst_time_us; size_t tries = 0; uint32_t val; @@ -233,6 +235,32 @@ val &= ~PCIE_INTX_ENABLE; write32p(conf->base + PCIE_INT_ENABLE_REG, val); + perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); + printk(BIOS_DEBUG, "%s: %lld us elapsed since assert PERST#\n", + __func__, perst_time_us); + + /* + * Described in PCIe CEM specification sections 2.2 + * (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + const uint64_t min_perst_time_us = 100000; /* 100 ms */ + if (perst_time_us < min_perst_time_us) { + if (!perst_time_us) { + printk(BIOS_WARNING, + "%s: PCIe early init data not found, sleeping 100ms\n", + __func__); + mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); + } else { + printk(BIOS_WARNING, + "%s: Need an extra %lld us delay to meet PERST# deassertion requirement\n", + __func__, min_perst_time_us - perst_time_us); + } + + udelay(min_perst_time_us - perst_time_us); + } + /* De-assert reset signals */ mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 1a17c6c..df347c0 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -6,6 +6,7 @@ #include <device/resource.h> #include <delay.h> #include <soc/addressmap.h> +#include <soc/early_init.h> #include <soc/gpio.h> #include <soc/pcie.h> #include <soc/pcie_common.h> @@ -72,4 +73,6 @@ /* Assert all reset signals at early stage */ mtk_pcie_reset(PCIE_RST_CTRL_REG, true); + + early_init_save_time(EARLY_INIT_PCIE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Pre-initialize PCIe at the bootblock stage
by Paul Fagerburg (Code Review) 29 Mar '22

29 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: mb/google/cherry: Pre-initialize PCIe at the bootblock stage ...................................................................... mb/google/cherry: Pre-initialize PCIe at the bootblock stage Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and waiting for 100ms, which is currently the only function of 'mtk_pcie_pre_init', so that the extra 100ms delay in ramstage is avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/bootblock.c M src/soc/mediatek/mt8195/Makefile.inc 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index c506caf..c811c4e 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -5,6 +5,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/i2c.h> +#include <soc/pcie.h> #include <soc/spi.h> #include "gpio.h" @@ -43,6 +44,13 @@ void bootblock_mainboard_init(void) { + /* + * Initialize PCIe pinmux and assert PERST# early to reduce + * the impact of 100ms delay. + */ + if (CONFIG(PCI)) + mtk_pcie_pre_init(); + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); nor_set_gpio_pinmux(); diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index b83fc32..0a305d9 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c +bootblock-$(CONFIG_PCI) += pcie.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 30 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add early init support
by Paul Fagerburg (Code Review) 29 Mar '22

29 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63020 ) Change subject: soc/mediatek/mt8195: Add early init support ...................................................................... soc/mediatek/mt8195: Add early init support Add early init support for MT8195 platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/include/soc/memlayout.ld 3 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 68fe0f3..b83fc32 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c +bootblock-y += ../common/early_init.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c @@ -53,6 +54,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += ../common/auxadc.c +ramstage-y += ../common/early_init.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c ramstage-y += ../common/dfd.c diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c index 3adf5c1..813c0c8 100644 --- a/src/soc/mediatek/mt8195/bootblock.c +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/early_init.h> #include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> @@ -14,4 +15,5 @@ mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); + early_init_clear(); } diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 5942776..e8b51d2 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -19,6 +19,9 @@ _ = ASSERT(size % 4K == 0, \ "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#define EARLY_INIT(addr, size) \ + REGION(early_init_data, addr, size, 4) + SECTIONS { SRAM_START(0x00100000) @@ -26,6 +29,7 @@ TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) + EARLY_INIT(0x00104010, 128) CBFS_MCACHE(0x00107c00, 8K) TIMESTAMP(0x00109c00, 1K) STACK(0x0010a000, 12K) 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Gerrit-Change-Number: 63020 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022