coreboot-gerrit March 2022

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Change in coreboot[master]: mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports
by Angel Pons (Code Review) 30 Mar '22

30 Mar '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63206 ) Change subject: mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports ...................................................................... mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports The PCH's PCIe ports do not support Gen3 speeds, only Gen1/Gen2. Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/63206/1 diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb index 30167f9..bfe453f 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb @@ -4,7 +4,7 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "sata_port_map" = "0x7" device pci 1c.4 on # PCIe Port #5 - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X" end device pci 1c.5 on end # PCIe Port #6 device pci 1c.6 on end # PCIe Port #7 diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb index 9452279..81133ee 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb @@ -5,10 +5,10 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "sata_port_map" = "0xf" device pci 1c.2 on # PCIe Port #3 - smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X" + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X" end device pci 1c.4 on # PCIe Port #5 - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X" end device pci 1c.5 on end # PCIe Port #6 device pci 1c.6 on end # PCIe Port #7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6 Gerrit-Change-Number: 63206 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/common: verify size of memchipinfo structure
by Shelley Chen (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Ravi Kumar Bokka, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63026 ) Change subject: soc/qualcomm/common: verify size of memchipinfo structure ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 16:55:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
by 9elements QA (Code Review) 30 Mar '22

30 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62954 ) Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo ...................................................................... Patch Set 12: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98106 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98105 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98104 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98103 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/98102 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98101 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/98100 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98099 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98098 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98097 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98096 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98095 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98094 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98093 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98092 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98091 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 12 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 16:29:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Updated Protectli fw6b documentations
by Paul Menzel (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Xue Yao. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63016 ) Change subject: Documentation: Updated Protectli fw6b documentations ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63016/comment/21d35717_88f67328 PS2, Line 9: ME cleaner has been tested on the fw6b. : More observations on the stock firmware has also been documented. : Compatible boards are listed along with the original manufacturer. As you enumerate the changes, please format it as a list. Patchset: PS2: Welcome, and thank you for updating the documentation. File Documentation/mainboard/protectli/fw6.md: https://review.coreboot.org/c/coreboot/+/63016/comment/87aacce3_30da971b PS2, Line 51: Protectli's official website Please add a link. https://review.coreboot.org/c/coreboot/+/63016/comment/03088cc4_87eeab12 PS2, Line 157: http://www.ylgkdn.cn/index.html Remove `index.html`? -- To view, visit https://review.coreboot.org/c/coreboot/+/63016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 2 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xue Yao <xueyao(a)xyte.ch> Gerrit-Comment-Date: Wed, 30 Mar 2022 16:06:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Updated Protectli fw6b documentations
by Xue Yao (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Xue Yao. Hello build bot (Jenkins), Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63016 to look at the new patch set (#2). Change subject: Documentation: Updated Protectli fw6b documentations ...................................................................... Documentation: Updated Protectli fw6b documentations ME cleaner has been tested on the fw6b. More observations on the stock firmware has also been documented. Compatible boards are listed along with the original manufacturer. Signed-off-by: Xue Yao <xueyao(a)xyte.ch> Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 --- M Documentation/mainboard/protectli/fw6.md 1 file changed, 23 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63016/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 2 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Xue Yao <xueyao(a)xyte.ch> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/starlabs/lite: Move Verb Table to variant directory
by 9elements QA (Code Review) 30 Mar '22

30 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62755 ) Change subject: mb/starlabs/lite: Move Verb Table to variant directory ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98055 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98054 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98053 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98052 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/98051 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98050 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/98049 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98048 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98047 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98046 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98045 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98044 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98043 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98042 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98041 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98040 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881 Gerrit-Change-Number: 62755 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:34:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/dptf/dptf.h: https://review.coreboot.org/c/coreboot/+/62944/comment/5cfbf2d3_e449dd0d PS5, Line 18: const char *tpwr_device_hid; > you should put this with https://review.coreboot. […] I can do that, but I thought this driver change(src/drivers/intel/dptf/dptf.h) and the soc change (src/soc/intel/alderlake/dptf.c) should be in separate patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:28:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/crota: init overridetree for crota
by Paul Fagerburg (Code Review) 30 Mar '22

30 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63022 ) Change subject: mb/google/brya/variants/crota: init overridetree for crota ...................................................................... mb/google/brya/variants/crota: init overridetree for crota init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf BUG=b:226315394 Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63022 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/crota/overridetree.cb 2 files changed, 311 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b3917d2..5261b66 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -179,6 +179,7 @@ config BOARD_GOOGLE_CROTA bool "-> Crota" select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_I2C_CS42L42 config BOARD_GOOGLE_MOLI bool "-> Moli" diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 4f2c04a..23d7f3c 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -1,6 +1,314 @@ +fw_config + field MB_SD 0 1 + option SD_ABSENT 0 + option SD_GL9750 1 + end + field KB_BL 2 2 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 3 5 + option AUDIO_UNKNOWN 0 + option MAX98360_CS42L42 1 + end + field DB_LTE 6 7 + option LTE_ABSENT 0 + option LTE_USB 1 + end +end + chip soc/intel/alderlake - device domain 0 on - end + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | | + #| I2C3 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2_C4 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2_C6 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_C8 + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + + device domain 0 on + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" + register "srcclk_pin" = "1" + device generic 0 alias emmc_rtd3 on end + end + # Enable PCIe-to-eMMC bridge PCIE 3 using clk 1 + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 BH799BB + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp6 off end #PCIE6 WWAN + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 1 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 1, + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref i2c0 on + chip drivers/i2c/cs42l42 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)" + register "ts_inv" = "true" + register "ts_dbnc_rise" = "RISE_DEB_1000_MS" + register "ts_dbnc_fall" = "FALL_DEB_0_MS" + register "btn_det_init_dbnce" = "100" + register "btn_det_event_dbnce" = "10" + register "bias_lvls[0]" = "15" + register "bias_lvls[1]" = "8" + register "bias_lvls[2]" = "4" + register "bias_lvls[3]" = "1" + register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_disable" = "true" + device i2c 48 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Gerrit-Change-Number: 63022 Gerrit-PatchSet: 10 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Hung-Te Lin (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Angel Pons, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 42: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/1ffb0c9b_3ea19083 PS42, Line 411: depends on PCI > I'm not a Kconfig build expert so not sure if that should be select or not... […] or, you should move/dupe the 'default y if ARCH_X86' to config PCI as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 42 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:12:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Hung-Te Lin (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Angel Pons, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 42: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/dd55f918_1498cd40 PS42, Line 411: depends on PCI > should this be 'depends on' or 'select'? […] I'm not a Kconfig build expert so not sure if that should be select or not... but you'll have to double check if the config will be changed on x86 or ARM. We would expect PCI/PCI_IO_OPS both being 'y' for x86 by default, and both 'n' for ARM (by default). -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 42 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:11:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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