coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Move WWAN power on sequence forward
by Paul Fagerburg (Code Review) 30 Mar '22

30 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63129 ) Change subject: mb/google/nissa/var/nivviks: Move WWAN power on sequence forward ...................................................................... mb/google/nissa/var/nivviks: Move WWAN power on sequence forward Move WWAN power on sequence from OS to coreboot. This can save the WWAN initial time about 10S. Another purpose is power resource be removed because we don't power off the LTE in S0ix. BUG=b:223490884 TEST=FM101-GL work as expected. Enumerate time from [ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module [ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 17.760224] usb 4-2: SerialNumber: 9c88998f to [ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module [ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 4.019762] usb 4-2: SerialNumber: 9c88998f Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c M src/mainboard/google/brya/variants/nivviks/gpio.c M src/mainboard/google/brya/variants/nivviks/overridetree.cb 3 files changed, 5 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index 60b0018..29698bc 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -232,7 +232,7 @@ /* F11 : NC */ PAD_NC(GPP_F11, NONE), /* F12 : GSXDOUT ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), + PAD_CFG_GPO(GPP_F12, 1, DEEP), /* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c index db3b9e3..6bb37b1 100644 --- a/src/mainboard/google/brya/variants/nivviks/gpio.c +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -32,10 +32,14 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index c870b37..610e990 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -304,11 +304,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)" - register "reset_off_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" - register "enable_delay_ms" = "20" device ref usb2_port4 on probe DB_USB DB_1C_LTE end -- To view, visit https://review.coreboot.org/c/coreboot/+/63129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1 Gerrit-Change-Number: 63129 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
by Paul Fagerburg (Code Review) 30 Mar '22

30 Mar '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63164 ) Change subject: mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR ...................................................................... mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. TEST=Build the coreboot for adlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 0d32746..20c37a0 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -1,6 +1,5 @@ config BOARD_INTEL_ADLRVP_COMMON def_bool n - select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID -- To view, visit https://review.coreboot.org/c/coreboot/+/63164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 Gerrit-Change-Number: 63164 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > weird, your patch train mess up this time. add HID should be the parent. Since tpwr_device_hid is defined in this patch, HID would be on top of this patch or else the build would be unstable. I tried the other way in the previous train and the HID patch would become unstable -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 13:10:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Add dram information to CBMEM table
by Ravi Kumar Bokka (Code Review) 30 Mar '22

30 Mar '22

Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc/qualcomm/common: Add dram information to CBMEM table ...................................................................... Patch Set 42: (4 comments) File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/59195/comment/11e3e07f_74b1c806 PS41, Line 37: if (sizeof(struct mem_chip_info) != 0) > What is this supposed to test, this can never be false? The thing you were supposed to check is `(te […] Taken care with below CL: https://review.coreboot.org/c/coreboot/+/63026 https://review.coreboot.org/c/coreboot/+/59195/comment/ed3b65ae_5d19cde2 PS41, Line 39: sizeof(struct mem_chip_info) > edit: sorry forgot to add that since this helper goes into a header file, it should be declared `sta […] Taken care with below CL: https://review.coreboot.org/c/coreboot/+/63026 https://review.coreboot.org/c/coreboot/+/59195/comment/63e0139b_4861e190 PS41, Line 43: sizeof(struct mem_chip_info) > Same here. Taken care with below CL: https://review.coreboot.org/c/coreboot/+/63026 https://review.coreboot.org/c/coreboot/+/59195/comment/4ac3e93b_e3f69c0a PS41, Line 174: mem_chip_addr, sizeof(mem_chip_addr) > This was supposed to be NULL and 0, and the comment above should clarify that the blob_address for t […] Taken care with below CL: https://review.coreboot.org/c/coreboot/+/63026 -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 13:10:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: verify size of memchipinfo structure
by Ravi Kumar Bokka (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63026 ) Change subject: soc/qualcomm/common: verify size of memchipinfo structure ...................................................................... Patch Set 3: (4 comments) Patchset: PS3: HI Julius, I have updated comments. please let me know if any thing i have missed here. Regards, Ravi File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/63026/comment/ba39bf13_6731340a PS1, Line 51: sizeof(struct mem_chip_info) > No you didn't. Done https://review.coreboot.org/c/coreboot/+/63026/comment/abb6a702_53200cbb PS1, Line 55: memchip > No you didn't. Done https://review.coreboot.org/c/coreboot/+/63026/comment/27fb61fe_81fedac0 PS1, Line 186: mem_chip_addr, sizeof(mem_chip_addr), 0); > No you didn't. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 13:09:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Eric Lai (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Varshit B Pandya, Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: weird, your patch train mess up this time. add HID should be the parent. -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 13:04:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Eric Lai (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 13:02:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Eric Lai (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 13:01:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add DPTF power participant for brya
by Eric Lai (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Varshit B Pandya, Rizwan Qureshi, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62947 ) Change subject: mb/google/brya: Add DPTF power participant for brya ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I463aa6fea6fdef9c9ae68d5425272d233c8c5743 Gerrit-Change-Number: 62947 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 12:58:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules
by Frans Hendriks (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Erik van den Bogaert, Patrick Rudolph, Lee Leahy. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62995 ) Change subject: drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Built and boot fine on facebook fbg1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/62995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc95a093cf86c834d63825bf76312ed21ec68215 Gerrit-Change-Number: 62995 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 12:45:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022