coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Hung-Te Lin (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Angel Pons, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 42: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/ca8d060a_4ed7325a PS42, Line 411: depends on PCI should this be 'depends on' or 'select'? if you do 'depends' and the PCI is default n, I think it won't be selected by default - e.g., you'll be changing the default behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 42 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RX
by Tim Wawrzynczak (Code Review) 30 Mar '22

30 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63174 ) Change subject: mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RX ...................................................................... mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RX Update the GPP_D12 according to USB_C3_LSX_RX. BUG=b:225081954 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The device can be recognized when it is attached in port3. localhost /sys/bus/thunderbolt/devices # ls 0-0 1-0 1-0:3.1 1-3 domain0 domain1 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/banshee/gpio.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index b8f4dab..ae37c90 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -101,7 +101,8 @@ /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG), - /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX */ + PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> NC */ PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d Gerrit-Change-Number: 63174 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
by Tim Wawrzynczak (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Zhuohao Lee, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63191 ) Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I think we could actually add a "power_gpio" to drivers/usb/acpi/chip. […] Does the kernel driver support D3cold? Could you try just this instead and see if it will do the same thing? ``` +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -244,6 +244,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 NFC"" register "type" = "UPC_TYPE_INTERNAL" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D3)" + register "has_power_resource" = "true" device ref usb2_port5 on end end chip drivers/usb/acpi ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Gerrit-Change-Number: 63191 Gerrit-PatchSet: 3 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:08:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Hung-Te Lin (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Angel Pons, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 42: (1 comment) Patchset: PS42: build failure on some models: - coreinfo.coreinfo - nvramcui.nvramcui Failures including: undefined reference to `pci_read_config8' -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 42 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:07:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
by Tim Wawrzynczak (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Zhuohao Lee, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63191 ) Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I think we could actually add a "power_gpio" to drivers/usb/acpi/chip.h and then add that to the power resource when generating the SSDT in usb_acpi.c. That should do the same thing, but in a less board-specific (read: hacky) way -- To view, visit https://review.coreboot.org/c/coreboot/+/63191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Gerrit-Change-Number: 63191 Gerrit-PatchSet: 3 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 15:04:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support for dojo
by Hung-Te Lin (Code Review) 30 Mar '22

30 Mar '22

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62360 ) Change subject: mb/google/cherry: Add PCIe domain support for dojo ...................................................................... mb/google/cherry: Add PCIe domain support for dojo Add override device tree for dojo and add PCIe domain support. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62360 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Kconfig A src/mainboard/google/cherry/variants/dojo/overridetree.cb 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 51ad029..206c4e4 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -71,4 +71,7 @@ endchoice +config OVERRIDE_DEVICETREE + default "variants/dojo/overridetree.cb" if BOARD_GOOGLE_DOJO + endif diff --git a/src/mainboard/google/cherry/variants/dojo/overridetree.cb b/src/mainboard/google/cherry/variants/dojo/overridetree.cb new file mode 100644 index 0000000..1dff594 --- /dev/null +++ b/src/mainboard/google/cherry/variants/dojo/overridetree.cb @@ -0,0 +1,22 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8195 + device domain 0 on + register "pcie_config" = "{ + .base = 0x112f0000, + .mmio_res_io = { + .cpu_addr = 0x20000000, + .pci_addr = 0x20000000, + .size = 16 * MiB, + .type = IORESOURCE_IO, + }, + .mmio_res_mem = { + .cpu_addr = 0x21000000, + .pci_addr = 0x21000000, + .size = 48 * MiB, + .type = IORESOURCE_MEM, + }, + }" + device pci 00.0 on end # - Host Bridge + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 28 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
by Tim Wawrzynczak (Code Review) 30 Mar '22

30 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62954 ) Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo ...................................................................... mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo Add thermal table settings for tarlo which shares the same firmware with taeko BUG=b:215033683 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 123 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index b4cda82..a2838b2 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -34,6 +34,10 @@ option BOOT_EMMC_DISABLED 0 option BOOT_EMMC_ENABLED 1 end + field THERMAL 16 + option THERMAL_FAN_TABLE_0 0 + option THERMAL_FAN_TABLE_1 1 + end field HPS 17 option HPS_ABSENT 0 option HPS_PRESENT 1 @@ -238,7 +242,125 @@ register "options.fan.fine_grained_control" = "1" register "options.fan.step_size" = "2" - device generic 0 alias dptf_policy on end + device generic 0 on + probe THERMAL THERMAL_FAN_TABLE_0 + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 74), + TEMP_PCT(75, 74), + TEMP_PCT(70, 74), + TEMP_PCT(65, 74), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(57, 70), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 39), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(57, 70), + TEMP_PCT(54, 50), + TEMP_PCT(48, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 39), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(57, 70), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 39), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 1 on + probe THERMAL THERMAL_FAN_TABLE_1 + end end end device ref pcie4_0 on 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 12 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Disable EN_SPKR on init
by Raul Rangel (Code Review) 30 Mar '22

30 Mar '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63145 ) Change subject: mb/google/guybrush: Disable EN_SPKR on init ...................................................................... mb/google/guybrush: Disable EN_SPKR on init We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot guybrush and verify the devbeep and gpio value in kernel Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147 Signed-off-by: Yu-Hsuan Hsu <yuhsuan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/variants/guybrush/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index cea1f42..f3ed09f 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -35,7 +35,7 @@ /* EN_PWR_FP */ PAD_GPO(GPIO_32, LOW), /* EN_SPKR */ - PAD_GPO(GPIO_31, HIGH), + PAD_GPO(GPIO_31, LOW), /* Unused TP27 */ PAD_NC(GPIO_70), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147 Gerrit-Change-Number: 63145 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/lite: Move Verb Table to variant directory
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62755 ) Change subject: mb/starlabs/lite: Move Verb Table to variant directory ...................................................................... mb/starlabs/lite: Move Verb Table to variant directory Move the verb table to variant directory to allow for different tables for different variants. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/lite/Makefile.inc M src/mainboard/starlabs/lite/variants/glk/Makefile.inc R src/mainboard/starlabs/lite/variants/glk/hda_verb.c 3 files changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/lite/Makefile.inc b/src/mainboard/starlabs/lite/Makefile.inc index 019d560..e7f8277 100644 --- a/src/mainboard/starlabs/lite/Makefile.inc +++ b/src/mainboard/starlabs/lite/Makefile.inc @@ -6,7 +6,6 @@ bootblock-y += bootblock.c ramstage-y += devtree.c -ramstage-y += hda_verb.c ramstage-y += mainboard.c ramstage-y += smbios.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/starlabs/lite/variants/glk/Makefile.inc b/src/mainboard/starlabs/lite/variants/glk/Makefile.inc index 05b0677..ae3ec84 100644 --- a/src/mainboard/starlabs/lite/variants/glk/Makefile.inc +++ b/src/mainboard/starlabs/lite/variants/glk/Makefile.inc @@ -3,5 +3,6 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += hda_verb.c romstage-y += romstage.c diff --git a/src/mainboard/starlabs/lite/hda_verb.c b/src/mainboard/starlabs/lite/variants/glk/hda_verb.c similarity index 100% rename from src/mainboard/starlabs/lite/hda_verb.c rename to src/mainboard/starlabs/lite/variants/glk/hda_verb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/62755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881 Gerrit-Change-Number: 62755 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Add GLKR variant
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62705 ) Change subject: ec/starlabs/merlin: Add GLKR variant ...................................................................... ec/starlabs/merlin: Add GLKR variant Add GLKR (N5030) Lite Mk IV variant Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/ec/starlabs/merlin/variants/glkr/ecdefs.h A src/ec/starlabs/merlin/variants/glkr/emem.asl A src/ec/starlabs/merlin/variants/glkr/events.asl 3 files changed, 266 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h new file mode 100644 index 0000000..51b34df --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <stdint.h> + +/* + * EC communication interface for Nuvoton Embedded Controller. + */ + +#ifndef _EC_STARLABS_GLKR_EC_DEFS_H +#define _EC_STARLABS_GLKR_EC_DEFS_H + +/* Nuvoton chip ID byte values. */ +#define NUVOTON_CHIPID_VAL 0x0004 + +/* EC RAM offsets. */ +#define ECRAM_TRACKPAD_STATE 0x14 +#define ECRAM_KBL_STATE 0x16 +#define ECRAM_KBL_BRIGHTNESS 0x17 +#define ECRAM_KBL_TIMEOUT 0x12 +#define ECRAM_FN_LOCK_STATE 0x15 +#define ECRAM_FN_CTRL_REVERSE 0x13 +#define ECRAM_MAX_CHARGE dead_code_t(uint8_t) +#define ECRAM_FAN_MODE dead_code_t(uint8_t) + +#endif diff --git a/src/ec/starlabs/merlin/variants/glkr/emem.asl b/src/ec/starlabs/merlin/variants/glkr/emem.asl new file mode 100644 index 0000000..d591358 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glkr/emem.asl @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + P0MV, 8, // PD Port 0 Major Version + P0SV, 8, // PD Port 0 Minor Version + P1MV, 8, // PD Port 1 Major Version + P1SV, 8, // PD Port 1 Minor Version + + Offset(0x0c), + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + + Offset(0x12), + KLTE, 8, // Keyboard Backlight Timeout + FCLA, 8, // Fn Ctrl Reverse + TPLE, 8, // Trackpad State + FLKE, 8, // Function Lock State + KLSE, 8, // Keyboard Backlight State + KLBE, 8, // Keyboard Backlight Brightness + + Offset(0x20), + RCMD, 8, // Send EC command + RCST, 8, // Status of EC command + + Offset(0x60), + TSE1, 8, // Sensor 1 Temperature + TSE2, 8, // Sensor 2 Temperature + TSE3, 8, // Sensor 3 Temperature + + Offset(0x63), + TSE4, 4, // Sensor 4 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + CHRA, 16, // Charge Rate + + Offset(0x72), + CHAR, 8, // Charger Temperature + + Offset(0x7e), + OSFG, 8, // OS Flag [TODO: Confirm] + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BT1A, 8, // Bt1 ASOC + BT1T, 16, // Bt1 Temperature + BT1C, 8, // Bt1 Control + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xa0), + BSNL, 8, // Battery Serial Number Low byte + BSNH, 8, // Battery Serial Number High Byte + BMN1, 8, // Battery Manufactory Name 1 + BMN2, 8, // Battery Manufactory Name 2 + BMN3, 8, // Battery Manufactory Name 3 + BMN4, 8, // Battery Manufactory Name 4 + BMN5, 8, // Battery Manufactory Name 5 + BMN6, 8, // Battery Manufactory Name 6 + BMN7, 8, // Battery Manufactory Name 7 + BMN8, 8, // Battery Manufactory Name 8 + BMN9, 8, // Battery Manufactory Name 9 + BMNA, 8, // Battery Manufactory Name 10 + BMNB, 8, // Battery Manufactory Name 11 + BMNC, 8, // Battery Manufactory Name 12 + BDN1, 8, // Battery Device Name 1 + BDN2, 8, // Battery Device Name 2 + BDN3, 8, // Battery Device Name 3 + BDN4, 8, // Battery Device Name 4 + BDN5, 8, // Battery Device Name 5 + BDN6, 8, // Battery Device Name 6 + BDN7, 8, // Battery Device Name 7 + BDN8, 8, // Battery Device Name 8 + BDN9, 8, // Battery Device Name 9 + BDNA, 8, // Battery Device Name 10 + BDNB, 8, // Battery Device Name 11 + BDNC, 8, // Battery Device Name 12 + BCT1, 8, // Battery Chemistry Type 1 + BCT2, 8, // Battery Chemistry Type 2 + BCT3, 8, // Battery Chemistry Type 3 + BCT4, 8, // Battery Chemistry Type 4 + BCT5, 8, // Battery Chemistry Type 5 + BCT6, 8, // Battery Chemistry Type 6 + + Offset(0xc0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xd0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xe0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F +} diff --git a/src/ec/starlabs/merlin/variants/glkr/events.asl b/src/ec/starlabs/merlin/variants/glkr/events.asl new file mode 100644 index 0000000..49589da --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glkr/events.asl @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q09, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q10, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q08, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_Q02, 0, NotSerialized) // Event: Turn off Backlight +{ + Printf ("EC: Backlight off") +} + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q60, 0, NotSerialized) // Event: Trackpad Enable +{ + Printf ("EC: Trackpad Enable") + SPC0 (0xD0C80600, 0x40800102) +} + +Method (_Q61, 0, NotSerialized) // Event: Trackpad Disable +{ + Printf ("EC: Trackpad Disable") + SPC0 (0xD0C80600, 0x40800200) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81 Gerrit-Change-Number: 62705 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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