coreboot-gerrit March 2022

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Jes Klinke, Christian Walter, Julius Werner. Hello build bot (Jenkins), Christian Walter, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63158 to look at the new patch set (#4). Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... tpm: Accept Google Ti50 TPM DID:VID A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h 5 files changed, 89 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63158/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 4 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask
by Karthik Ramasubramanian (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63222 ) Change subject: soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Gerrit-Change-Number: 63222 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 30 Mar 2022 20:48:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63222 ) Change subject: soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask ...................................................................... soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask When masking out bits with an and mask, the bit mask needs to be inverted. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 --- M src/soc/amd/common/block/i2c/i23c_pad_ctrl.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63222/1 diff --git a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c index 36211a3..2439054 100644 --- a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c +++ b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c @@ -48,7 +48,7 @@ pad_ctrl |= speed == I2C_SPEED_STANDARD ? I23C_PAD_CTRL_FALLSLEW_SEL_STD : I23C_PAD_CTRL_FALLSLEW_SEL_LOW; - pad_ctrl &= I23C_PAD_CTRL_SLEW_N_MASK; + pad_ctrl &= ~I23C_PAD_CTRL_SLEW_N_MASK; pad_ctrl |= I23C_PAD_CTRL_SLEW_N_FAST; misc_write32(MISC_I23C_PAD_CTRL(bus), pad_ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/63222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Gerrit-Change-Number: 63222 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Improve build flow
by build bot (Jenkins) (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56119 ) Change subject: security/intel/cbnt/Makefile.inc: Improve build flow ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Gerrit-Change-Number: 56119 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 30 Mar 2022 20:38:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics
by build bot (Jenkins) (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56118 ) Change subject: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41bbdabf7b846386651e64f4afb5b7b9fb38e1cb Gerrit-Change-Number: 56118 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 20:36:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/Makefile.inc: Do some cosmetics
by build bot (Jenkins) (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Arthur Heymans, Jason Glenesk, Martin Roth, Marshall Dawson, Fred Reitberger. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56117 ) Change subject: soc/amd/*/Makefile.inc: Do some cosmetics ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Gerrit-Change-Number: 56117 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 20:36:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Add the x86 bootblock as a regular cbfs file
by build bot (Jenkins) (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Arthur Heymans, Martin Roth, Julius Werner, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56122 ) Change subject: Makefile.inc: Add the x86 bootblock as a regular cbfs file ...................................................................... Patch Set 5: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Gerrit-Change-Number: 56122 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 20:24:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/fast_spi: Refactor ROM caching implementation
by Subrata Banik (Code Review) 30 Mar '22

30 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63221 ) Change subject: soc/intel/common/block/fast_spi: Refactor ROM caching implementation ...................................................................... soc/intel/common/block/fast_spi: Refactor ROM caching implementation This patch removes different implementation to cache the SPI ROM between early and later boot stage where SPI ROM caching doesn't need even advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage is always mapped to below 4GB hence, simple `set_var_mtrr()` function can be sufficient without any additional complexity. BUG=b:225766934 TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able to update the temporary variable range MTRRs and showed ~44ms of boot time savings as below: Before: 90:starting to load payload 1,084,052 (14) 15:starting LZMA decompress (ignore for x86) 1,084,121 (68) 16:finished LZMA decompress (ignore for x86) 1,140,742 (56,620) After: 90:starting to load payload 1,090,433 (14) 15:starting LZMA decompress (ignore for x86) 1,090,650 (217) 16:finished LZMA decompress (ignore for x86) 1,102,896 (12,245) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63221/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 7be71a2..be0e319 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -196,6 +196,16 @@ write32(spibar + SPIBAR_RESET_LOCK, ssl); } +static void fast_spi_enable_cache_range(unsigned int base, unsigned int size) +{ + const int type = MTRR_TYPE_WRPROT; + int mtrr = get_free_var_mtrr(); + if (mtrr == -1) + return; + + set_var_mtrr(mtrr, base, size, type); +} + /* * Returns bios_start and fills in size of the BIOS region. */ @@ -240,19 +250,11 @@ { size_t ext_bios_size; uintptr_t ext_bios_base; - const int type = MTRR_TYPE_WRPROT; if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size)) return; - if (ENV_PAYLOAD_LOADER) { - mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); - } else { - int mtrr = get_free_var_mtrr(); - if (mtrr == -1) - return; - set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); - } + fast_spi_enable_cache_range(ext_bios_base, ext_bios_size); } void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf) @@ -271,7 +273,6 @@ { size_t bios_size; uint32_t alignment; - const int type = MTRR_TYPE_WRPROT; uintptr_t base; /* Only the IFD BIOS region is memory mapped (at top of 4G) */ @@ -290,16 +291,7 @@ bios_size = ALIGN_UP(bios_size, alignment); base = 4ULL*GiB - bios_size; - if (ENV_PAYLOAD_LOADER) { - mtrr_use_temp_range(base, bios_size, type); - } else { - int mtrr = get_free_var_mtrr(); - - if (mtrr == -1) - return; - - set_var_mtrr(mtrr, base, bios_size, type); - } + fast_spi_enable_cache_range(base, bios_size); /* Check if caching is needed for extended bios region if supported */ fast_spi_cache_ext_bios_window(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e Gerrit-Change-Number: 63221 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr: Delay removing `temp` variable range MTRR snapshot
by Subrata Banik (Code Review) 30 Mar '22

30 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63220 ) Change subject: cpu/x86/mtrr: Delay removing `temp` variable range MTRR snapshot ...................................................................... cpu/x86/mtrr: Delay removing `temp` variable range MTRR snapshot This patch delays removing `temporray` MTRR snapshots to avoid conflicts with other operations attached with same `BS_PAYLOAD_BOOT/BS_ON_EXIT` boot state. BUG=b:225766934 TEST=Having variable MTRR snapshot using display_mtrrs() is able to list only the permanent MTRRs and all temporary MTRRs are removed prior to boot to payload. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I602dca989745159d013d6573191861b296f5d3ab --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/63220/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 84d844a..89cac7f 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -915,4 +915,4 @@ } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, remove_temp_solution, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, remove_temp_solution, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, remove_temp_solution, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/63220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I602dca989745159d013d6573191861b296f5d3ab Gerrit-Change-Number: 63220 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: {cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR count
by Subrata Banik (Code Review) 30 Mar '22

30 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63219 ) Change subject: {cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR count ...................................................................... {cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR count This patch replaces the implementation that is used to get the number of variable MTRRs with `get_var_mtrr_count()` function. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c --- M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/mtrr.c M src/cpu/x86/mtrr/xip_cache.c M src/drivers/amd/agesa/mtrr_fixme.c 4 files changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63219/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 1f1f968..81c987b 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -247,11 +247,9 @@ int num_var_mtrrs; struct saved_msr *msr_entry; int i; - msr_t msr; /* Determine number of MTRRs need to be saved. */ - msr = rdmsr(MTRR_CAP_MSR); - num_var_mtrrs = msr.lo & 0xff; + num_var_mtrrs = get_var_mtrr_count(); /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE. */ msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 185014e..84d844a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -41,11 +41,7 @@ static void detect_var_mtrrs(void) { - msr_t msr; - - msr = rdmsr(MTRR_CAP_MSR); - - total_mtrrs = msr.lo & 0xff; + total_mtrrs = get_var_mtrr_count(); if (total_mtrrs > NUM_MTRR_STATIC_STORAGE) { printk(BIOS_WARNING, diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c index cd82e4f..6ed96af 100644 --- a/src/cpu/x86/mtrr/xip_cache.c +++ b/src/cpu/x86/mtrr/xip_cache.c @@ -14,8 +14,7 @@ the MTRR, no matter the caching type, are filled and not overlapping. */ static uint32_t max_cache_used(void) { - msr_t msr = rdmsr(MTRR_CAP_MSR); - int i, total_mtrrs = msr.lo & MTRR_CAP_VCNT; + int i, total_mtrrs = get_var_mtrr_count(); uint32_t total_cache = 0; for (i = 0; i < total_mtrrs; i++) { diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index c589553..1313b5d 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -14,8 +14,7 @@ { int i, max_var_mtrrs; msr_t msr; - msr = rdmsr(MTRR_CAP_MSR); - max_var_mtrrs = msr.lo & MTRR_CAP_VCNT; + max_var_mtrrs = get_var_mtrr_count(); for (i = 0; i < max_var_mtrrs; i++) { msr = rdmsr(MTRR_PHYS_MASK(i)); -- To view, visit https://review.coreboot.org/c/coreboot/+/63219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c Gerrit-Change-Number: 63219 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022