coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt
by Karthik Ramasubramanian (Code Review) 31 Mar '22

31 Mar '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63132 ) Change subject: mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt ...................................................................... mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt Add the specific SPD hex file for the Samsung memory part with updating the part number into the SPD table. The ABL needs to identify the part by checking SPD data to do the proper tuning. BUG=b:224884904 TEST=Build, validate the SPD data has been applied. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- A src/mainboard/google/guybrush/variants/dewatt/memory/K4U6E3S4AB-MGCL.hex A src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc 3 files changed, 66 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/K4U6E3S4AB-MGCL.hex b/src/mainboard/google/guybrush/variants/dewatt/memory/K4U6E3S4AB-MGCL.hex new file mode 100644 index 0000000..639d81f --- /dev/null +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/K4U6E3S4AB-MGCL.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 04 08 00 00 00 00 02 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 4B 34 55 36 45 33 53 +34 41 42 2D 4D 47 43 4C 00 00 00 00 00 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex b/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex new file mode 100644 index 0000000..00b26e6 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 94 08 00 00 00 00 0A 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 48 34 55 42 45 33 44 +34 41 42 2D 4D 47 43 4C 00 00 00 00 00 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index c4e409d..9c4a7e4 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -13,6 +13,6 @@ SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 6(0b0110) SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 7(0b0111) SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 8(0b1000) -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL +SPD_SOURCES += $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/K4U6E3S4AB-MGCL.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 10(0b1010) -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 11(0b1011) Parts = K4UBE3D4AB-MGCL +SPD_SOURCES += $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/K4UBE3D4AB-MGCL.hex # ID = 11(0b1011) Parts = K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/63132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94 Gerrit-Change-Number: 63132 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [NEEDTEST]soc/intel/apl: Drop cbfs bootblock
by Arthur Heymans (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Sean Rhodes, Andrey Petrov. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63225 ) Change subject: [NEEDTEST]soc/intel/apl: Drop cbfs bootblock ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/apollolake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63225/comment/31272b08_a3577d23 PS1, Line 154: 0x40 use 64 too... -- To view, visit https://review.coreboot.org/c/coreboot/+/63225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Gerrit-Change-Number: 63225 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:34:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus: Constify i2c_busdev and i2c_link
by Tim Wawrzynczak (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Raul Rangel, Matt DeVillier, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63208 ) Change subject: device/i2c_bus: Constify i2c_busdev and i2c_link ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: +Karthik and Raul, this is the patch train that Matt and I worked out for fixing b/121309055, which also fixes TS & TP for mainline Linux and Windows as well -- To view, visit https://review.coreboot.org/c/coreboot/+/63208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If795087ecdaea24ad7834dcc6d5bf6a72f2aea8f Gerrit-Change-Number: 63208 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:31:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Docs/project_ideas: Implement the ARM BBR spec in coreboot
by Julius Werner (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Arthur Heymans, Felix Singer, Angel Pons, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63034 ) Change subject: Docs/project_ideas: Implement the ARM BBR spec in coreboot ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File Documentation/contributing/project_ideas.md: https://review.coreboot.org/c/coreboot/+/63034/comment/3f24274d_b0dc8600 PS1, Line 232: ## Make coreboot ARM (L)BBR compliant > Done Sorry for the delay, but yes, it looks better now, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:30:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/timestamp_serialized: Add timestamp enum to name mapping
by Julius Werner (Code Review) 31 Mar '22

31 Mar '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62709 ) Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping ...................................................................... commonlib/timestamp_serialized: Add timestamp enum to name mapping Some solutions require readable form of timestamps, which does not contain spaces. Current descriptive timestamp names do not meet this criteria. Also, mapping enums to their text representation allows for quick grepping (use of grep command) to find relevant timestamps in the code. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62709 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 139 insertions(+), 132 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index a51b68f..890d988 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -4,6 +4,7 @@ #define __TIMESTAMP_SERIALIZED_H__ #include <stdint.h> +#include <commonlib/bsd/helpers.h> struct timestamp_entry { uint32_t entry_id; @@ -165,152 +166,158 @@ TS_KERNEL_DECOMPRESSION = 1102, }; +#define TS_NAME_DEF(id, desc) {(id), STRINGIFY(id), (desc)} + static const struct timestamp_id_to_name { uint32_t id; + const char *enum_name; const char *name; } timestamp_ids[] = { /* Marker to report base_time. */ - { 0, "1st timestamp" }, - { TS_ROMSTAGE_START, "start of romstage" }, - { TS_INITRAM_START, "before RAM initialization" }, - { TS_INITRAM_END, "after RAM initialization" }, - { TS_ROMSTAGE_END, "end of romstage" }, - { TS_VBOOT_START, "start of verified boot" }, - { TS_VBOOT_END, "end of verified boot" }, - { TS_COPYRAM_START, "starting to load ramstage" }, - { TS_COPYRAM_END, "finished loading ramstage" }, - { TS_RAMSTAGE_START, "start of ramstage" }, - { TS_BOOTBLOCK_START, "start of bootblock" }, - { TS_BOOTBLOCK_END, "end of bootblock" }, - { TS_COPYROM_START, "starting to load romstage" }, - { TS_COPYROM_END, "finished loading romstage" }, - { TS_ULZMA_START, "starting LZMA decompress (ignore for x86)" }, - { TS_ULZMA_END, "finished LZMA decompress (ignore for x86)" }, - { TS_ULZ4F_START, "starting LZ4 decompress (ignore for x86)" }, - { TS_ULZ4F_END, "finished LZ4 decompress (ignore for x86)" }, - { TS_DEVICE_ENUMERATE, "device enumeration" }, - { TS_DEVICE_CONFIGURE, "device configuration" }, - { TS_DEVICE_ENABLE, "device enable" }, - { TS_DEVICE_INITIALIZE, "device initialization" }, - { TS_OPROM_INITIALIZE, "Option ROM initialization" }, - { TS_OPROM_COPY_END, "Option ROM copy done" }, - { TS_OPROM_END, "Option ROM run done" }, - { TS_DEVICE_DONE, "device setup done" }, - { TS_CBMEM_POST, "cbmem post" }, - { TS_WRITE_TABLES, "write tables" }, - { TS_FINALIZE_CHIPS, "finalize chips" }, - { TS_LOAD_PAYLOAD, "starting to load payload" }, - { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, - { TS_SELFBOOT_JUMP, "selfboot jump" }, - { TS_DELAY_START, "Forced delay start" }, - { TS_DELAY_END, "Forced delay end" }, - { TS_READ_UCODE_START, "started reading uCode" }, - { TS_READ_UCODE_END, "finished reading uCode" }, - { TS_ELOG_INIT_START, "started elog init" }, - { TS_ELOG_INIT_END, "finished elog init" }, + {0, "TS_START", "1st timestamp"}, + TS_NAME_DEF(TS_ROMSTAGE_START, "start of romstage"), + TS_NAME_DEF(TS_INITRAM_START, "before RAM initialization"), + TS_NAME_DEF(TS_INITRAM_END, "after RAM initialization"), + TS_NAME_DEF(TS_ROMSTAGE_END, "end of romstage"), + TS_NAME_DEF(TS_VBOOT_START, "start of verified boot"), + TS_NAME_DEF(TS_VBOOT_END, "end of verified boot"), + TS_NAME_DEF(TS_COPYRAM_START, "starting to load ramstage"), + TS_NAME_DEF(TS_COPYRAM_END, "finished loading ramstage"), + TS_NAME_DEF(TS_RAMSTAGE_START, "start of ramstage"), + TS_NAME_DEF(TS_BOOTBLOCK_START, "start of bootblock"), + TS_NAME_DEF(TS_BOOTBLOCK_END, "end of bootblock"), + TS_NAME_DEF(TS_COPYROM_START, "starting to load romstage"), + TS_NAME_DEF(TS_COPYROM_END, "finished loading romstage"), + TS_NAME_DEF(TS_ULZMA_START, "starting LZMA decompress (ignore for x86)"), + TS_NAME_DEF(TS_ULZMA_END, "finished LZMA decompress (ignore for x86)"), + TS_NAME_DEF(TS_ULZ4F_START, "starting LZ4 decompress (ignore for x86)"), + TS_NAME_DEF(TS_ULZ4F_END, "finished LZ4 decompress (ignore for x86)"), + TS_NAME_DEF(TS_DEVICE_ENUMERATE, "device enumeration"), + TS_NAME_DEF(TS_DEVICE_CONFIGURE, "device configuration"), + TS_NAME_DEF(TS_DEVICE_ENABLE, "device enable"), + TS_NAME_DEF(TS_DEVICE_INITIALIZE, "device initialization"), + TS_NAME_DEF(TS_OPROM_INITIALIZE, "Option ROM initialization"), + TS_NAME_DEF(TS_OPROM_COPY_END, "Option ROM copy done"), + TS_NAME_DEF(TS_OPROM_END, "Option ROM run done"), + TS_NAME_DEF(TS_DEVICE_DONE, "device setup done"), + TS_NAME_DEF(TS_CBMEM_POST, "cbmem post"), + TS_NAME_DEF(TS_WRITE_TABLES, "write tables"), + TS_NAME_DEF(TS_FINALIZE_CHIPS, "finalize chips"), + TS_NAME_DEF(TS_LOAD_PAYLOAD, "starting to load payload"), + TS_NAME_DEF(TS_ACPI_WAKE_JUMP, "ACPI wake jump"), + TS_NAME_DEF(TS_SELFBOOT_JUMP, "selfboot jump"), + TS_NAME_DEF(TS_POSTCAR_START, "start of postcar"), + TS_NAME_DEF(TS_POSTCAR_END, "end of postcar"), + TS_NAME_DEF(TS_DELAY_START, "Forced delay start"), + TS_NAME_DEF(TS_DELAY_END, "Forced delay end"), + TS_NAME_DEF(TS_READ_UCODE_START, "started reading uCode"), + TS_NAME_DEF(TS_READ_UCODE_END, "finished reading uCode"), + TS_NAME_DEF(TS_ELOG_INIT_START, "started elog init"), + TS_NAME_DEF(TS_ELOG_INIT_END, "finished elog init"), - { TS_COPYVER_START, "starting to load verstage" }, - { TS_COPYVER_END, "finished loading verstage" }, - { TS_TPMINIT_START, "starting to initialize TPM" }, - { TS_TPMINIT_END, "finished TPM initialization" }, - { TS_VERIFY_SLOT_START, "starting to verify keyblock/preamble (RSA)" }, - { TS_VERIFY_SLOT_END, "finished verifying keyblock/preamble (RSA)" }, - { TS_HASH_BODY_START, "starting to verify body (load+SHA2+RSA) " }, - { TS_LOADING_END, "finished loading body" }, - { TS_HASHING_END, "finished calculating body hash (SHA2)" }, - { TS_HASH_BODY_END, "finished verifying body signature (RSA)" }, - { TS_TPMPCR_START, "starting TPM PCR extend" }, - { TS_TPMPCR_END, "finished TPM PCR extend" }, - { TS_TPMLOCK_START, "starting locking TPM" }, - { TS_TPMLOCK_END, "finished locking TPM" }, - { TS_TPM_ENABLE_UPDATE_START, "started TPM enable update" }, - { TS_TPM_ENABLE_UPDATE_END, "finished TPM enable update" }, - - { TS_COPYVPD_START, "starting to load Chrome OS VPD" }, - { TS_COPYVPD_RO_END, "finished loading Chrome OS VPD (RO)" }, - { TS_COPYVPD_RW_END, "finished loading Chrome OS VPD (RW)" }, - - { TS_EC_SYNC_START, "starting EC software sync" }, - { TS_EC_HASH_READY, "EC vboot hash ready" }, - { TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" }, - { TS_EC_SYNC_END, "finished EC software sync" }, - - { TS_DC_START, "depthcharge start" }, - { TS_RO_PARAMS_INIT, "RO parameter init" }, - { TS_RO_VB_INIT, "RO vboot init" }, - { TS_RO_VB_SELECT_FIRMWARE, "RO vboot select firmware" }, - { TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel" }, - { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" }, - { TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" }, - { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, - { TS_VB_STORAGE_INIT_DONE, "finished storage device initialization" }, - { TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" }, - { TS_VB_VBOOT_DONE, "finished vboot kernel verification" }, - { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, - { TS_KERNEL_START, "jumping to kernel" }, + /* Google related timestamps */ + TS_NAME_DEF(TS_COPYVER_START, "starting to load verstage"), + TS_NAME_DEF(TS_COPYVER_END, "finished loading verstage"), + TS_NAME_DEF(TS_TPMINIT_START, "starting to initialize TPM"), + TS_NAME_DEF(TS_TPMINIT_END, "finished TPM initialization"), + TS_NAME_DEF(TS_VERIFY_SLOT_START, "starting to verify keyblock/preamble (RSA)"), + TS_NAME_DEF(TS_VERIFY_SLOT_END, "finished verifying keyblock/preamble (RSA)"), + TS_NAME_DEF(TS_HASH_BODY_START, "starting to verify body (load+SHA2+RSA) "), + TS_NAME_DEF(TS_LOADING_END, "finished loading body"), + TS_NAME_DEF(TS_HASHING_END, "finished calculating body hash (SHA2)"), + TS_NAME_DEF(TS_HASH_BODY_END, "finished verifying body signature (RSA)"), + TS_NAME_DEF(TS_TPMPCR_START, "starting TPM PCR extend"), + TS_NAME_DEF(TS_TPMPCR_END, "finished TPM PCR extend"), + TS_NAME_DEF(TS_TPMLOCK_START, "starting locking TPM"), + TS_NAME_DEF(TS_TPMLOCK_END, "finished locking TPM"), + TS_NAME_DEF(TS_EC_SYNC_START, "starting EC software sync"), + TS_NAME_DEF(TS_EC_HASH_READY, "EC vboot hash ready"), + TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw"), + TS_NAME_DEF(TS_EC_SYNC_END, "finished EC software sync"), + TS_NAME_DEF(TS_COPYVPD_START, "starting to load Chrome OS VPD"), + TS_NAME_DEF(TS_COPYVPD_RO_END, "finished loading Chrome OS VPD (RO)"), + TS_NAME_DEF(TS_COPYVPD_RW_END, "finished loading Chrome OS VPD (RW)"), + TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, "started TPM enable update"), + TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, "finished TPM enable update"), /* AMD related timestamps */ - { TS_AGESA_INIT_RESET_START, "calling AmdInitReset" }, - { TS_AGESA_INIT_RESET_END, "back from AmdInitReset" }, - { TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" }, - { TS_AGESA_INIT_EARLY_END, "back from AmdInitEarly" }, - { TS_AGESA_INIT_POST_START, "calling AmdInitPost" }, - { TS_AGESA_INIT_POST_END, "back from AmdInitPost" }, - { TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" }, - { TS_AGESA_INIT_ENV_END, "back from AmdInitEnv" }, - { TS_AGESA_INIT_MID_START, "calling AmdInitMid" }, - { TS_AGESA_INIT_MID_END, "back from AmdInitMid" }, - { TS_AGESA_INIT_LATE_START, "calling AmdInitLate" }, - { TS_AGESA_INIT_LATE_END, "back from AmdInitLate" }, - { TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" }, - { TS_AGESA_INIT_RTB_END, "back from AmdInitRtb/AmdS3Save" }, - { TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" }, - { TS_AGESA_INIT_RESUME_END, "back from AmdInitResume" }, - { TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" }, - { TS_AGESA_S3_LATE_END, "back from AmdS3LateRestore" }, - { TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" }, - { TS_AGESA_S3_FINAL_END, "back from AmdS3FinalRestore" }, - { TS_AMD_APOB_READ_START, "starting APOB read" }, - { TS_AMD_APOB_ERASE_START, "starting APOB erase" }, - { TS_AMD_APOB_WRITE_START, "starting APOB write" }, - { TS_AMD_APOB_END, "finished APOB" }, + TS_NAME_DEF(TS_AGESA_INIT_RESET_START, "calling AmdInitReset"), + TS_NAME_DEF(TS_AGESA_INIT_RESET_END, "back from AmdInitReset"), + TS_NAME_DEF(TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly"), + TS_NAME_DEF(TS_AGESA_INIT_EARLY_END, "back from AmdInitEarly"), + TS_NAME_DEF(TS_AGESA_INIT_POST_START, "calling AmdInitPost"), + TS_NAME_DEF(TS_AGESA_INIT_POST_END, "back from AmdInitPost"), + TS_NAME_DEF(TS_AGESA_INIT_ENV_START, "calling AmdInitEnv"), + TS_NAME_DEF(TS_AGESA_INIT_ENV_END, "back from AmdInitEnv"), + TS_NAME_DEF(TS_AGESA_INIT_MID_START, "calling AmdInitMid"), + TS_NAME_DEF(TS_AGESA_INIT_MID_END, "back from AmdInitMid"), + TS_NAME_DEF(TS_AGESA_INIT_LATE_START, "calling AmdInitLate"), + TS_NAME_DEF(TS_AGESA_INIT_LATE_END, "back from AmdInitLate"), + TS_NAME_DEF(TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save"), + TS_NAME_DEF(TS_AGESA_INIT_RTB_END, "back from AmdInitRtb/AmdS3Save"), + TS_NAME_DEF(TS_AGESA_INIT_RESUME_START, "calling AmdInitResume"), + TS_NAME_DEF(TS_AGESA_INIT_RESUME_END, "back from AmdInitResume"), + TS_NAME_DEF(TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore"), + TS_NAME_DEF(TS_AGESA_S3_LATE_END, "back from AmdS3LateRestore"), + TS_NAME_DEF(TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore"), + TS_NAME_DEF(TS_AGESA_S3_FINAL_END, "back from AmdS3FinalRestore"), + TS_NAME_DEF(TS_AMD_APOB_READ_START, "starting APOB read"), + TS_NAME_DEF(TS_AMD_APOB_ERASE_START, "starting APOB erase"), + TS_NAME_DEF(TS_AMD_APOB_WRITE_START, "starting APOB write"), + TS_NAME_DEF(TS_AMD_APOB_END, "finished APOB"), /* Intel ME related timestamps */ - { TS_ME_INFORM_DRAM_START, "waiting for ME acknowledgement of raminit"}, - { TS_ME_INFORM_DRAM_END, "finished waiting for ME response"}, - { TS_ME_END_OF_POST_START, "before sending EOP to ME"}, - { TS_ME_END_OF_POST_END, "after sending EOP to ME"}, - { TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"}, - { TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"}, - { TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"}, - { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, - { TS_CSE_FW_SYNC_START, "starting CSE firmware sync"}, - { TS_CSE_FW_SYNC_END, "finished CSE firmware sync"}, - { TS_ME_ROM_START, "CSME ROM started execution"}, + TS_NAME_DEF(TS_ME_INFORM_DRAM_START, "waiting for ME acknowledgement of raminit"), + TS_NAME_DEF(TS_ME_INFORM_DRAM_END, "finished waiting for ME response"), + TS_NAME_DEF(TS_ME_END_OF_POST_START, "before sending EOP to ME"), + TS_NAME_DEF(TS_ME_END_OF_POST_END, "after sending EOP to ME"), + TS_NAME_DEF(TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"), + TS_NAME_DEF(TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"), + TS_NAME_DEF(TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"), + TS_NAME_DEF(TS_ME_RECEIVED_CRDA_FROM_PMC, + "CSE received 'CPU Reset Done Ack sent' from PMC"), + TS_NAME_DEF(TS_CSE_FW_SYNC_START, "starting CSE firmware sync"), + TS_NAME_DEF(TS_CSE_FW_SYNC_END, "finished CSE firmware sync"), /* FSP related timestamps */ - { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, - { TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" }, - { TS_FSP_TEMP_RAM_EXIT_START, "calling FspTempRamExit" }, - { TS_FSP_TEMP_RAM_EXIT_END, "returning from FspTempRamExit" }, - { TS_FSP_SILICON_INIT_START, "calling FspSiliconInit" }, - { TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" }, - { TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit" }, - { TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit" }, - { TS_FSP_ENUMERATE_START, "calling FspNotify(AfterPciEnumeration)" }, - { TS_FSP_ENUMERATE_END, - "returning from FspNotify(AfterPciEnumeration)" }, - { TS_FSP_FINALIZE_START, "calling FspNotify(ReadyToBoot)" }, - { TS_FSP_FINALIZE_END, "returning from FspNotify(ReadyToBoot)" }, - { TS_FSP_END_OF_FIRMWARE_START, "calling FspNotify(EndOfFirmware)" }, - { TS_FSP_END_OF_FIRMWARE_END, - "returning from FspNotify(EndOfFirmware)" }, + TS_NAME_DEF(TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit"), + TS_NAME_DEF(TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit"), + TS_NAME_DEF(TS_FSP_TEMP_RAM_EXIT_START, "calling FspTempRamExit"), + TS_NAME_DEF(TS_FSP_TEMP_RAM_EXIT_END, "returning from FspTempRamExit"), + TS_NAME_DEF(TS_FSP_SILICON_INIT_START, "calling FspSiliconInit"), + TS_NAME_DEF(TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit"), + TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit"), + TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit"), + TS_NAME_DEF(TS_FSP_ENUMERATE_START, "calling FspNotify(AfterPciEnumeration)"), + TS_NAME_DEF(TS_FSP_ENUMERATE_END, "returning from FspNotify(AfterPciEnumeration)"), + TS_NAME_DEF(TS_FSP_FINALIZE_START, "calling FspNotify(ReadyToBoot)"), + TS_NAME_DEF(TS_FSP_FINALIZE_END, "returning from FspNotify(ReadyToBoot)"), + TS_NAME_DEF(TS_FSP_END_OF_FIRMWARE_START, "calling FspNotify(EndOfFirmware)"), + TS_NAME_DEF(TS_FSP_END_OF_FIRMWARE_END, "returning from FspNotify(EndOfFirmware)"), + TS_NAME_DEF(TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M"), + TS_NAME_DEF(TS_FSP_SILICON_INIT_LOAD, "loading FSP-S"), - { TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M" }, - { TS_FSP_SILICON_INIT_LOAD, "loading FSP-S" }, + /* Intel ME continued */ + TS_NAME_DEF(TS_ME_ROM_START, "CSME ROM started execution"), - { TS_POSTCAR_START, "start of postcar" }, - { TS_POSTCAR_END, "end of postcar" }, + /* Depthcharge entry timestamp */ + TS_NAME_DEF(TS_DC_START, "depthcharge start"), + + TS_NAME_DEF(TS_RO_PARAMS_INIT, "RO parameter init"), + TS_NAME_DEF(TS_RO_VB_INIT, "RO vboot init"), + TS_NAME_DEF(TS_RO_VB_SELECT_FIRMWARE, "RO vboot select firmware"), + TS_NAME_DEF(TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel"), + + TS_NAME_DEF(TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel"), + + TS_NAME_DEF(TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel"), + TS_NAME_DEF(TS_VB_EC_VBOOT_DONE, "finished EC verification"), + TS_NAME_DEF(TS_VB_STORAGE_INIT_DONE, "finished storage device initialization"), + TS_NAME_DEF(TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk"), + TS_NAME_DEF(TS_VB_VBOOT_DONE, "finished vboot kernel verification"), + + TS_NAME_DEF(TS_KERNEL_START, "jumping to kernel"), + TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation"), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/62709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Gerrit-Change-Number: 62709 Gerrit-PatchSet: 11 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib/bsd/helpers: Remove redundancy with libpayload defines
by Julius Werner (Code Review) 31 Mar '22

31 Mar '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62921 ) Change subject: commonlib/bsd/helpers: Remove redundancy with libpayload defines ...................................................................... commonlib/bsd/helpers: Remove redundancy with libpayload defines Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h Remove redundant defines from libpayload.h and libpayloads' standard headers. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/drivers/video/graphics.c M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/stddef.h M payloads/libpayload/include/stdlib.h M src/commonlib/bsd/include/commonlib/bsd/helpers.h M src/include/string.h 6 files changed, 8 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 7f08d40..632a283 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -57,7 +57,6 @@ #define PIVOT_H_MASK (PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT) #define PIVOT_V_MASK (PIVOT_V_TOP|PIVOT_V_CENTER|PIVOT_V_BOTTOM) #define ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) -#define ABS(x) ((x) < 0 ? -(x) : (x)) static char initialized = 0; diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 90aeeeb..24c48c1 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -46,6 +46,7 @@ #include <libpayload-config.h> #include <cbgfx.h> #include <commonlib/bsd/fmap_serialized.h> +#include <commonlib/bsd/helpers.h> #include <commonlib/bsd/mem_chip_info.h> #include <ctype.h> #include <die.h> @@ -67,33 +68,8 @@ #include <pci.h> #include <archive.h> -/* Double-evaluation unsafe min/max, for bitfields and outside of functions */ -#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) -#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) -#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) - -#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ - __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ - __TYPEOF_UNLESS_CONST(b, a) var_b = (b); \ - var_a op var_b ? var_a : var_b; \ -}) - -#define __CMP(a, b, op) __builtin_choose_expr( \ - __builtin_constant_p(a) && __builtin_constant_p(b), \ - __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) - -#define MIN(a, b) __CMP(a, b, <) -#define MAX(a, b) __CMP(a, b, >) - -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define BIT(x) (1ul << (x)) -#define DIV_ROUND_UP(x, y) ({ \ - typeof(x) _div_local_x = (x); \ - typeof(y) _div_local_y = (y); \ - (_div_local_x + _div_local_y - 1) / _div_local_y; \ -}) - static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; } #define LITTLE_ENDIAN 1234 diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index e127345..fb6ec9b 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -2,6 +2,7 @@ #define _STDDEF_H #include <arch/types.h> +#include <commonlib/bsd/helpers.h> #ifndef __WCHAR_TYPE__ #define __WCHAR_TYPE__ int @@ -22,22 +23,6 @@ typedef __SIZE_TYPE__ ssize_t; #undef unsigned -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *) 0)->MEMBER) -#define member_size(TYPE, MEMBER) (sizeof(((TYPE *) 0)->MEMBER)) - -#define check_member(structure, member, offset) _Static_assert( \ - offsetof(struct structure, member) == offset, \ - "`struct " #structure "` offset for `" #member "` is not " #offset) - -/* Standard units. */ -#define KiB (1 << 10) -#define MiB (1 << 20) -#define GiB (1 << 30) - -#define KHz (1000) -#define MHz (1000*KHz) -#define GHz (1000*MHz) - #define NSECS_PER_SEC 1000000000 #define USECS_PER_SEC 1000000 #define MSECS_PER_SEC 1000 diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index eb014f4..18f1dca 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -34,12 +34,6 @@ #include <stddef.h> #include <string.h> -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) -#define ALIGN_UP(x,a) ALIGN((x),(a)) -#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) -#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) - /** * @defgroup malloc Memory allocation functions * @{ diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h index 733b05a..4995305 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/helpers.h +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -126,4 +126,10 @@ #define retry(attempts, condition, ...) \ _retry_impl(attempts, condition, __VA_ARGS__) +/* Stringify a token */ +#ifndef STRINGIFY +#define _STRINGIFY(x) #x +#define STRINGIFY(x) _STRINGIFY(x) +#endif + #endif /* COMMONLIB_BSD_HELPERS_H */ diff --git a/src/include/string.h b/src/include/string.h index 3cfa18d..f595c7e 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -7,12 +7,6 @@ #include <stddef.h> #include <stdio.h> -/* Stringify a token */ -#ifndef STRINGIFY -#define _STRINGIFY(x) #x -#define STRINGIFY(x) _STRINGIFY(x) -#endif - void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); -- To view, visit https://review.coreboot.org/c/coreboot/+/62921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Gerrit-Change-Number: 62921 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbmem: Add FlameGraph-compatible timestamps output
by Julius Werner (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Jakub Czapiga, Tim Wawrzynczak, Paul Menzel, Alex Levin, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62474 ) Change subject: util/cbmem: Add FlameGraph-compatible timestamps output ...................................................................... Patch Set 16: Code-Review+2 (2 comments) Patchset: PS16: LGTM after one more nit File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/62474/comment/715aecc4_3e8aca52 PS16, Line 1585: print_defaults Well you don't need this now. -- To view, visit https://review.coreboot.org/c/coreboot/+/62474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 Gerrit-Change-Number: 62474 Gerrit-PatchSet: 16 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:21:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Improve build flow
by build bot (Jenkins) (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56119 ) Change subject: security/intel/cbnt/Makefile.inc: Improve build flow ...................................................................... Patch Set 8: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Gerrit-Change-Number: 56119 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:12:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics
by build bot (Jenkins) (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56118 ) Change subject: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics ...................................................................... Patch Set 8: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41bbdabf7b846386651e64f4afb5b7b9fb38e1cb Gerrit-Change-Number: 56118 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:12:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/Makefile.inc: Do some cosmetics
by build bot (Jenkins) (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Arthur Heymans, Jason Glenesk, Martin Roth, Marshall Dawson, Fred Reitberger. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56117 ) Change subject: soc/amd/*/Makefile.inc: Do some cosmetics ...................................................................... Patch Set 8: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Gerrit-Change-Number: 56117 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:12:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022