coreboot-gerrit March 2022

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Change in coreboot[master]: [NEEDTEST]soc/amd/non-car: Don't add bootblock cbfs file
by Arthur Heymans (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63226 ) Change subject: [NEEDTEST]soc/amd/non-car: Don't add bootblock cbfs file ...................................................................... [NEEDTEST]soc/amd/non-car: Don't add bootblock cbfs file The bootblock.elf file gets embedded in the BIOSPSP part and loaded by the PSP in dram. The top aligned bootblock in cbfs is unused. Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/63226/1 diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 7f50965..003a8e0 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -20,6 +20,10 @@ if SOC_AMD_COMMON_BLOCK_NONCAR +config TOP_ALIGNED_CBFS_BOOTBLOCK + bool + default n + config MEMLAYOUT_LD_FILE string default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" -- To view, visit https://review.coreboot.org/c/coreboot/+/63226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187 Gerrit-Change-Number: 63226 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NEEDTEST]soc/intel/apl: Drop cbfs bootblock
by Arthur Heymans (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Andrey Petrov. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63225 ) Change subject: [NEEDTEST]soc/intel/apl: Drop cbfs bootblock ...................................................................... [NEEDTEST]soc/intel/apl: Drop cbfs bootblock The bootblock is loaded from IFWI so there is no need to have it in cbfs. Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63225/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 91d203e..2c0436d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -414,4 +414,8 @@ config INTEL_GMA_BCLM_WIDTH default 32 +config TOP_ALIGNED_CBFS_BOOTBLOCK + bool + default n + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 29ef9e5..b9618f1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -146,6 +146,14 @@ $(CBFSTOOL) $< write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward endif +$(obj)/fit_placeholder: + dd if=/dev/zero of=$@ bs=64 count=1 &>/dev/null + +cbfs-files-y += fit_pointer +fit_pointer-file := $(obj)/fit_placeholder +fit_pointer-position := -0x40 +fit_pointer-type := "cbfs header" + # DSP firmware settings files. ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/glk/nhlt-blobs -- To view, visit https://review.coreboot.org/c/coreboot/+/63225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Gerrit-Change-Number: 63225 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apl: Write to cbfs regions using intermediate targets
by Arthur Heymans (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Andrey Petrov. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63224 ) Change subject: soc/intel/apl: Write to cbfs regions using intermediate targets ...................................................................... soc/intel/apl: Write to cbfs regions using intermediate targets There is no need to after all files have been added. This also adds messages when adding the files. Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Makefile.inc 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63224/1 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1335090..29ef9e5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -122,8 +122,9 @@ cp $(CONFIG_LBP2_FILE_NAME) $@ endif -files_added:: $(objcbfs)/lbp2.bin - $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $< --fill-upward +$(call add_intermediate, write_lbp2, $(objcbfs)/lbp2.bin) + @printf " FMAP writing lbp2 to %s\n" $(CONFIG_LBP2_FMAP_NAME) + $(CBFSTOOL) $< write -r $(CONFIG_LBP2_FMAP_NAME) -f $< --fill-upward endif # Bootblock on Apollolake platform lies in the IFWI region. In order to place @@ -137,11 +138,12 @@ # b. Using cbfstool: # 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME. ifeq ($(CONFIG_NEED_IFWI),y) -files_added:: $(IFWITOOL) +$(call add_intermediate, write_ifwi, $(objcbfs)/bootblock.bin $(IFWITOOL)) + @printf " IFWI Embedding %s in %s\n" $(objcbfs)/bootblock.bin $(CONFIG_IFWI_FMAP_NAME) $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL - $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward + $(CBFSTOOL) $< write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward endif # DSP firmware settings files. -- To view, visit https://review.coreboot.org/c/coreboot/+/63224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Gerrit-Change-Number: 63224 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile.inc: Add the x86 bootblock as a regular cbfs file
by Arthur Heymans (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Arthur Heymans, Martin Roth, Julius Werner, Yu-Ping Wu. Hello build bot (Jenkins), Martin Roth, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56122 to look at the new patch set (#6). Change subject: Makefile.inc: Add the x86 bootblock as a regular cbfs file ...................................................................... Makefile.inc: Add the x86 bootblock as a regular cbfs file Files of type bootblock are now always top aligned. This assumes only x86 ever uses cbfs file type bootblock. As the cbfs header needs to be at a specific place and it can be updated only later on, use a placeholder cbfs file. Some platforms don't need a top aligned bootblock in cbfs like Intel APL or modern AMD platforms as the bootblock is loaded differently. Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/Kconfig M src/arch/x86/Makefile.inc 3 files changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56122/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Gerrit-Change-Number: 56122 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_V...
by 9elements QA (Code Review) 31 Mar '22

31 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56803 ) Change subject: util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_VERSION ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98177 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98176 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98175 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98174 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/98173 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98172 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/98171 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98170 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98169 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98168 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98167 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98166 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98165 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98164 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98163 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98162 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/56803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e Gerrit-Change-Number: 56803 Gerrit-PatchSet: 5 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:05:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: x86: mmio: Qualify variables as volatile
by Julius Werner (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62828 ) Change subject: x86: mmio: Qualify variables as volatile ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > There is no garantee in the C standard that '(type *)CONSTANT' will actually point to the hardware […] Sounds like GCC just fixed this issue and backported it to gcc-11.3: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 Maybe we should consider uprevving crossgcc to include that fix? -- To view, visit https://review.coreboot.org/c/coreboot/+/62828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2769bb0e365aa9d82d709d3715323819bc9de6e Gerrit-Change-Number: 62828 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:04:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Christian Walter, Julius Werner, Jett Rink. Hello build bot (Jenkins), Christian Walter, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63158 to look at the new patch set (#6). Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... tpm: Accept Google Ti50 TPM DID:VID A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h 5 files changed, 92 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63158/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 6 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jett Rink <jettrink(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Christian Walter, Julius Werner, Jett Rink. Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... Patch Set 5: (3 comments) Patchset: PS5: Julius, could you also take a look at this. I think it is ready for official review now. File src/drivers/tpm/cr50.c: https://review.coreboot.org/c/coreboot/+/63158/comment/edd39581_75c5ff43 PS3, Line 67: if (version->type != GSC_CR50) > should we have a `printk` info here like down below in the function? Done https://review.coreboot.org/c/coreboot/+/63158/comment/f4ff6300_96928457 PS3, Line 214: ver->minor = 42; > why 42? if this is a placeholder, then we should have a TODO comment Yes, after debate about what string format Ti50 wants to support, the conclusion was that the existing parsing method can be used. -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 5 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jett Rink <jettrink(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 20:53:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jett Rink <jettrink(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [Test] [Do not Merge] Add typedef for wchar_t
by Anil Kumar K (Code Review) 30 Mar '22

30 Mar '22

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63223 ) Change subject: [Test] [Do not Merge] Add typedef for wchar_t ...................................................................... [Test] [Do not Merge] Add typedef for wchar_t Change-Id: I10f4d5f09c0b1d5a4bfc8c75a2d4995fc8639580 --- M util/cbfstool/ProcessorBind.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/63223/1 diff --git a/util/cbfstool/ProcessorBind.h b/util/cbfstool/ProcessorBind.h index aa7f407..d7e6b13 100644 --- a/util/cbfstool/ProcessorBind.h +++ b/util/cbfstool/ProcessorBind.h @@ -43,6 +43,8 @@ /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. /// typedef uint16_t CHAR16; + +typedef uint16_t wchar_t; /// /// 2-byte signed value. /// -- To view, visit https://review.coreboot.org/c/coreboot/+/63223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10f4d5f09c0b1d5a4bfc8c75a2d4995fc8639580 Gerrit-Change-Number: 63223 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Christian Walter, Julius Werner. Hello build bot (Jenkins), Christian Walter, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63158 to look at the new patch set (#5). Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... tpm: Accept Google Ti50 TPM DID:VID A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h 5 files changed, 92 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63158/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 5 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022