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Change subject: mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARS
......................................................................
Patch Set 2: Code-Review+2
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Subrata Banik has uploaded a new patch set (#2) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/61602 )
Change subject: soc/intel/crashlog: Temporarily remove to reorganize
......................................................................
soc/intel/crashlog: Temporarily remove to reorganize
Since there is some copy-pasting between the ADL and TGL drivers,
a refactoring would be helpful. In addition, the drivers are a great
candidate for becoming coreboot PCI drivers based on the CRASHLOG
and SRAM PCI devices. In order to ease review of the final patches,
and the final flow, this patch removes the current crashlog code,
which will be reintroduced in different places in the following
patches.
Change-Id: I7d4a5995c8d330e560ed923ed2b9ccca243604c0
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M configs/config.google_volteer.build_test_purposes
M src/mainboard/google/brya/Kconfig.name
M src/soc/intel/alderlake/Makefile.inc
D src/soc/intel/alderlake/crashlog.c
D src/soc/intel/alderlake/include/soc/crashlog.h
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/common/Kconfig.common
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/Makefile.inc
M src/soc/intel/common/block/acpi/acpi_bert.c
D src/soc/intel/common/block/crashlog/Makefile.inc
D src/soc/intel/common/block/crashlog/crashlog.c
D src/soc/intel/common/block/include/intelblocks/crashlog.h
M src/soc/intel/tigerlake/Makefile.inc
D src/soc/intel/tigerlake/crashlog_lib.c
D src/soc/intel/tigerlake/include/soc/crashlog.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
17 files changed, 14 insertions(+), 1,464 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/61602/2
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Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 )
Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
Patch Set 25:
(2 comments)
File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h:
https://review.coreboot.org/c/coreboot/+/59193/comment/97fa4e1c_224e12fc
PS24, Line 6: typedef
> Just make it a struct mem_chip_info, do not typedef. […]
hi julius, thanks for your comment. i will take care in next push
https://review.coreboot.org/c/coreboot/+/59193/comment/271faae3_d1643bda
PS24, Line 7: uint8_t type;
> There should also be an enum somewhere in this file that defines the possible values for this `type` […]
hi julius, thanks for your comment. i will take care in next push
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57784 )
Change subject: device: Add pciexp_find_next_extended_cap function
......................................................................
Patch Set 4:
(7 comments)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/57784/comment/43476971_0afaa974
PS2, Line 2:
> @Tim, Can you please check below code refactoring if it helps […]
Ack
https://review.coreboot.org/c/coreboot/+/57784/comment/c5a1d71d_6fe56a63
PS2, Line 34: unsigned int pciexp_find_next_extended_cap(struct device *dev, unsigned int cap,
: unsigned int pos)
> +1 to simplification. […]
Ack
https://review.coreboot.org/c/coreboot/+/57784/comment/9973dd13_139e16f4
PS2, Line 40: Read the passed-in capability to get the pointer to next
> In `pci_s_find_next_capability()`, it looks like the function always starts from the PCI_CAPABILITY_ […]
Ack
https://review.coreboot.org/c/coreboot/+/57784/comment/ebc64bb9_837adb66
PS2, Line 42: this_cap_offset
> Shouldn't this be checked for 0 before reading the cap?
Ack
https://review.coreboot.org/c/coreboot/+/57784/comment/4562dda5_5750a380
PS2, Line 45: if (!this_cap_offset || !this_cap)
: return 0;
:
> This isn't possible given while requirements on line 44.
Ack
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/57784/comment/2fdcc215_43bcd09b
PS3, Line 17:
> tab ?
Ack
https://review.coreboot.org/c/coreboot/+/57784/comment/7d05d0a1_3026cfa2
PS3, Line 37: }
> Nit: Add a blank line between functions.
Ack
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Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak.
Subrata Banik has uploaded a new patch set (#4) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/57784 )
Change subject: device: Add pciexp_find_next_extended_cap function
......................................................................
device: Add pciexp_find_next_extended_cap function
Some PCIe devices have extended capability lists that contain
multiples instances of the same capability. This patch provides a
function similar to pciexp_find_extended_cap that can be used to
search through multiple instances of the same capability by returning
the offset of the next extended capability of the given type following
the passed-in offset. The base functionality of searching for a given
capability from an offset is extracted to a local helper function and
both pciexp_find_extended_cap and pciexp_find_next_extended_cap use
this helper.
Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/device/pciexp_device.c
M src/include/device/pciexp.h
2 files changed, 23 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57784/4
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/eafd34b6_bc000ebb
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> > Hmm, I mean remove SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE, an […]
Yeah agreed with Subrata here - current naming conventions are aligned to FSP API calls, just simple snd straightforward to let users to choose.
Create additional kconfig like CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH just create even more confusion for no apparent reason.
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Subrata Banik has uploaded a new patch set (#4) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/57787 )
Change subject: soc/intel/common: Add Crash Log and PMC SRAM PCI device IDs
......................................................................
soc/intel/common: Add Crash Log and PMC SRAM PCI device IDs
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device
IDs.
Document Number: 619501, 645548
Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/sram/sram.c
2 files changed, 12 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/57787/4
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57787 )
Change subject: soc/intel/common: Add crashlog SRAM PCI device IDs for TGL-U/Y and ADL-P
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57787/comment/b51ba8f6_186d905a
PS2, Line 7: oc/intel/common: Add crashlog SRAM PCI device IDs for TGL-U/Y and ADL-P
> soc/intel/common/{ADL-P, TGL}: Add crashlog SRAM PCI device IDs
Ack
File src/soc/intel/common/block/sram/sram.c:
https://review.coreboot.org/c/coreboot/+/57787/comment/3deee71c_8742b5f2
PS2, Line 41: PCI_DEVICE_ID_INTEL_TGP_PMC_CRASHLOG_SRAM,
> care to add PCI_DEVICE_ID_INTEL_ADP_P_PMC_CRASHLOG_SRAM as well ?
Ack
https://review.coreboot.org/c/coreboot/+/57787/comment/4c6f0027_0395fcbe
PS2, Line 41: PCI_DEVICE_ID_INTEL_TGP_PMC_CRASHLOG_SRAM,
> care to add PCI_DEVICE_ID_INTEL_ADP_P_PMC_CRASHLOG_SRAM as well ?
Ack
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Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/3ae2f922_ab0d8499
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> Hmm, I mean remove SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE, and bring entire code (covered by these 2 flags) under CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH.
We can't drop `SKIP_` as we would still SoC user to take decision about either calling FSP-NotifyPhase of native cb driver. Hence, we need provide those choice to user.
>
> >From SoC recommendation side, Ready to Boot and End of Post are event which has meaning and silicon prefer to perform some operation under specific hoods, hence, coreboot would allow the same flexibility for SoC vendor enggs to add the required code inside specific `if` clause without mixing it.
>
> From the code perspective, both the flags are getting executed sequentially and not as two disjoint events.
Even thats the case with FSP-NotifyPhase API call as well today, Please check the log below:
NotifyPhaseApi() - Begin [Phase: 00000040]
FSP Ready To Boot ...
......
NotifyPhaseApi() - End [Status: 0x00000000]
PROGRESS CODE: V0000487F I0
PROGRESS CODE: V00002800 I0
NotifyPhaseApi() - Begin [Phase: 000000F0]
FSP End of Firmware ...
......
NotifyPhaseApi() - End [Status: 0x00000000]
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