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Change subject: mb/google/var/banshee: Add gpios to lock
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/var/anahera4es: Add gpios to lock
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61558
to look at the new patch set (#3).
Change subject: soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/efs_fmap_check.c
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61558/3
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Change subject: mb/google/var/agah: Add gpios to lock
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/i2c/tpm/cr50.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140335):
https://review.coreboot.org/c/coreboot/+/61721/comment/be0ee524_6312d3b0
PS1, Line 592: if (cr50_i2c_write(CR50_BOARD_CFG(0), (uint8_t *)&board_cfg_value, sizeof(board_cfg_value)))
line over 96 characters
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Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
TODO: measure boot time impact
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61637 )
Change subject: soc/mediatek/mt8173/dramc_pi_calibration_api.c: Remove duplicated "ERROR" in log message
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Thx
File src/soc/mediatek/mt8173/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/61637/comment/d761e40d_bbb66fa6
PS1, Line 594: error
> nit: what about changing this to […]
Done
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61722 )
Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
......................................................................
mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/mainboard.c
2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/61722/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 386aa11..04c8f6a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -44,6 +44,7 @@
select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
select SOC_INTEL_ALDERLAKE_PCH_P
select SYSTEM_TYPE_LAPTOP
+ select CR50_USE_LONG_INTERRUPT_PULSES
config BOARD_GOOGLE_BASEBOARD_BRASK
def_bool n
diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 536eabc..3496cf6 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -2,9 +2,13 @@
#include <baseboard/variants.h>
#include <device/device.h>
+#include <drivers/i2c/tpm/tpm.h>
#include <ec/ec.h>
#include <soc/ramstage.h>
#include <fw_config.h>
+#include <security/tpm/tss.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
{
@@ -24,6 +28,29 @@
void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
+ int ret;
+
+ ret = tlcl_lib_init();
+ if (ret != VB2_SUCCESS) {
+ printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+ return;
+ }
+
+ if (cr50_is_long_interrupt_pulse_enabled()) {
+ printk(BIOS_INFO, "Enabling GPIO PM b/c CR50 has long IRQ pulse support\n");
+ config->gpio_override_pm = 0;
+ } else {
+ printk(BIOS_INFO, "Disabling GPIO PM b/c CR50 does not have long IRQ pulse "
+ "support\n");
+ config->gpio_override_pm = 1;
+ config->gpio_pm[COMM_0] = 0;
+ config->gpio_pm[COMM_1] = 0;
+ config->gpio_pm[COMM_2] = 0;
+ config->gpio_pm[COMM_3] = 0;
+ config->gpio_pm[COMM_4] = 0;
+ config->gpio_pm[COMM_5] = 0;
+ }
+
variant_update_soc_chip_config(config);
}
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