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Change subject: sc7280: Disable fingerprint sensor feature as its not present on device
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
So no Qualcomm reference boards have the FP sensor? If that's the case, then can we just remove all this code?
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
Patch Set 3:
(3 comments)
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/61721/comment/171d3202_95a1eb5a
PS3, Line 535: 0.5.5 / 0.6.5
Why are there two versions?
https://review.coreboot.org/c/coreboot/+/61721/comment/611e02f5_34644796
PS3, Line 547: cr50_get_board_cfg
Maybe name this "cr50_get_board_cfg_features()" to avoid confusion like occurred on line 574 since this does not return the entire board_cfg value?
https://review.coreboot.org/c/coreboot/+/61721/comment/6ed3f1cd_94db45e2
PS3, Line 574: if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) {
This isn't going to work because cr50_get_board_cfg() strips off that bit prior to returning board config.
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Change subject: src/lib: Add CBMEM tag id to parse ddr information
......................................................................
Patch Set 27: Code-Review+1
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Change subject: mb/google/brya/variants/brask: Enable Bluetooth offload support
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61404/comment/3b44e076_52a568e8
PS2, Line 13: t
nit: remove this extra letter
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 16:
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/59507/comment/ef9da449_079f22c2
PS15, Line 160: if (CONFIG(SOC_INTEL_CSE_PRE_CPU_TELEMETRY))
: cse_get_telemetry_data();
> Thanks, I will check that.
Done
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Change subject: device: Add support for PCIe Resizable BARs
......................................................................
Patch Set 3:
(3 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/61215/comment/5b84ab52_3d265f96
PS3, Line 643: in preference of
> NIT - this reads a bit confusing. […]
Done
https://review.coreboot.org/c/coreboot/+/61215/comment/fe614e83_aea7e6b3
PS3, Line 660: )
> NIT - end with a period.
Done
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/61215/comment/3b21c81f_c08e47a0
PS3, Line 351: 4
> Should this be assigned a shift value constant like those below (eg. […]
I added a few more comments to what is going on here. Basically there are two bitmasks that are intended to be concatenated together, but they belong to two different registers, therefore this reads them and then shifts them over to where they will form the contiguous bitmask they are supposed to be.
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Hello build bot (Jenkins), Nico Huber, Subrata Banik, Angel Pons, Nick Vaccaro, Arthur Heymans, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61215
to look at the new patch set (#4).
Change subject: device: Add support for PCIe Resizable BARs
......................................................................
device: Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.
When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.
This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.
BUG=b:214443809
TEST=compile (device with this capability not available yet),
also verify that no changes are seen in resource allocation for
google/brya0 before and after this change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf
---
M src/device/Kconfig
M src/device/pci_device.c
M src/include/device/pci_def.h
M src/include/device/resource.h
4 files changed, 183 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/61215/4
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Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/apollolake: Add function to clear PMCON status bits
......................................................................
Patch Set 2: Code-Review+2
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