Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61645 )
Change subject: mb/google/guybrush: Fix trackpad SCI config
......................................................................
mb/google/guybrush: Fix trackpad SCI config
Trackpad GPIO configuration does not align with the IRQ configuration
in the devicetree. Configure the trackpad GPIO to generate SCI on
falling edge.
BUG=None
TEST=Build and boot to OS in Nipperkin. Ensure the trackpad is
functional. Suspend the device and wake it using trackpad. Perform
suspend/resume sequence for 100 iterations.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: If4324e09535d2676c8a8c6643604227eeaba0fe8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61645
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Jon Murphy <jpmurphy(a)google.com>
Reviewed-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
Rob Barnes: Looks good to me, approved
Jon Murphy: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index fbbe1f9..fff98d2 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -28,7 +28,7 @@
/* EN_PWR_WWAN_X */
PAD_GPO(GPIO_8, HIGH),
/* SOC_TCHPAD_INT_ODL */
- PAD_SCI(GPIO_9, PULL_NONE, EDGE_HIGH),
+ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
/* S0A3 */
PAD_NF(GPIO_10, S0A3, PULL_NONE),
/* SOC_FP_RST_L */
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61721 )
Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/61721/comment/c2ab4c81_13e27c7c
PS4, Line 568: (board_cfg_value == CR50_BOARD_CFG_VALUE)
> ((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE)
Done
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
The cr50 BOARD_CFG register has a bit to support extended interrupt
pulses to the PCH. There is support for this in the SPI driver, but
not in the I2C driver, and it may be required for some boards,
therefore port the logic over to the I2C driver.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I9fcfed9fa133db2560c4a855376d249e865c1335
---
M src/drivers/i2c/tpm/cr50.c
M src/drivers/i2c/tpm/tpm.h
A src/soc/intel/common/TMP.txt
3 files changed, 96 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/61721/5
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61559 )
Change subject: soc/amd/sabrina: Move EFS into FMAP section
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/amd/chausie/board.fmd:
https://review.coreboot.org/c/coreboot/+/61559/comment/984123f4_868fad50
PS1, Line 4: 3M
> In the next patch, I set it so that this option is not enabled for ChromeOS
if i understood things correctly, there is a requirement to use the first possible efs location on sabrina. the fmap ro/rwa/rwb partitions then has to be adapted accordingly. if the ro fmap section is at the beginning, we can still put the efs into the ro cbfs
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
Patch Set 4:
(2 comments)
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/61721/comment/64823586_c0c85a94
PS3, Line 535: 0.5.5 / 0.6.5
> IIRC, 0.5 is Pre-prod, 0.6 is prod (you can find the same logic in src/drivers/spi/tpm/tpm. […]
Ack
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/61721/comment/01fced7a_4e5865e4
PS4, Line 568: (board_cfg_value == CR50_BOARD_CFG_VALUE)
((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE)
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Change subject: soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
+Reka and Kangheui as FYI
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
Patch Set 3:
(3 comments)
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/61721/comment/01b53b53_f0ed8fa4
PS3, Line 535: 0.5.5 / 0.6.5
> Why are there two versions?
IIRC, 0.5 is Pre-prod, 0.6 is prod (you can find the same logic in src/drivers/spi/tpm/tpm.c)
https://review.coreboot.org/c/coreboot/+/61721/comment/328b22f5_13917db4
PS3, Line 547: cr50_get_board_cfg
> Maybe name this "cr50_get_board_cfg_features()" to avoid confusion like occurred on line 574 since t […]
Removed the mask instead, I don't think it helps anything here.
https://review.coreboot.org/c/coreboot/+/61721/comment/d82c2c14_aff8554a
PS3, Line 574: if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) {
> This isn't going to work because cr50_get_board_cfg() strips off that bit prior to returning board c […]
good catch! I will fix the logic up. The mask is actually not really helping anything.
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Hello build bot (Jenkins), Subrata Banik, Christian Walter, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61721
to look at the new patch set (#4).
Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
The cr50 BOARD_CFG register has a bit to support extended interrupt
pulses to the PCH. There is support for this in the SPI driver, but
not in the I2C driver, and it may be required for some boards,
therefore port the logic over to the I2C driver.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I9fcfed9fa133db2560c4a855376d249e865c1335
---
M src/drivers/i2c/tpm/cr50.c
M src/drivers/i2c/tpm/tpm.h
2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/61721/4
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