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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/i2c/tpm/cr50.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140345):
https://review.coreboot.org/c/coreboot/+/61721/comment/898d8938_c349cead
PS2, Line 587: if (cr50_i2c_write(CR50_BOARD_CFG(0), (uint8_t *)&board_cfg_value, sizeof(board_cfg_value)))
line over 96 characters
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Change subject: device: Add support for PCIe Resizable BARs
......................................................................
Patch Set 3: Code-Review+2
(3 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/61215/comment/e2cfc67a_96a36f47
PS3, Line 643: in preference of
NIT - this reads a bit confusing. Maybe "in preference to" or "in preference over"?
https://review.coreboot.org/c/coreboot/+/61215/comment/603b91d5_5f7a88e2
PS3, Line 660: )
NIT - end with a period.
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/61215/comment/70c026c2_c3a195ed
PS3, Line 351: 4
Should this be assigned a shift value constant like those below (eg. line 373)?
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Change subject: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/61678/comment/f0ec3560_eeaa580b
PS1, Line 658: * Disable the energy efficient turbo mode */
: s_cfg->EnergyEfficientTurbo = 0;
> With this feature, CPU doesn't hit turbo frequency when needed. […]
Sure, but power and performance need to be verified.
Also referring to the implementation again, this is just a bit in MSR_POWER_CTL, could we just move to a patch more like this?
```
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a5543d6364..1271f971fb 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -559,6 +559,9 @@ struct soc_intel_alderlake_config {
* Default 0. Setting this to 1 enable CNVi DDR RFIM.
*/
bool CnviDdrRfim;
+
+ /* Control whether "Energy-Efficient Turbo" is enabled or not (MSR_POWER_CTL) */
+ bool energy_efficient_turbo;
};
typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 426f6216b6..caac3482e9 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -67,10 +67,12 @@ static void configure_misc(void)
msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
- /* Enable PROCHOT */
+ /* Enable PROCHOT and energy-efficient turbo */
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
msr.lo |= (1 << 23); /* Lock it */
+ if (!conf->energy_efficient_turbo)
+ msr.lo |= (1 << 19); /* Set the Disable Energy Efficient Turbo bit. */
wrmsr(MSR_POWER_CTL, msr);
}
```
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Change subject: mb/amd/chausie: Move EFS into FMAP section
......................................................................
mb/amd/chausie: Move EFS into FMAP section
The chausie mainboard uses the first 128kByte of SPI flash for the EC
firmware. The EFS/amdfw should be placed at the 128kByte offset. Due to
this, there is no room for the CBFS headers. The
AMD_SOC_SEPARATE_EFS_SECTION option is used to locate the EFS/amdfw via
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
The cr50 BOARD_CFG register has a bit to support extended interrupt
pulses to the PCH. There is support for this in the SPI driver, but
not in the I2C driver, and it may be required for some boards,
therefore port the logic over to the I2C driver.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I9fcfed9fa133db2560c4a855376d249e865c1335
---
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Change subject: soc/amd/sabrina: Move EFS into FMAP section
......................................................................
soc/amd/sabrina: Move EFS into FMAP section
The chausie mainboard uses the first 128kByte of SPI flash for the EC
firmware. The EFS/amdfw should be placed at the 128kByte offset. Due to
this, there is no room for the CBFS headers. The
AMD_SOC_SEPARATE_EFS_SECTION option is used to locate the EFS/amdfw via
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This patch adds support of AMD_SOC_SEPARATE_EFS_SECTION to sabrina
Change-Id: Ifa9333f4097705a5c572756ac3ead3ae7a0b22a4
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Change subject: drivers/i2c/tpm/cr50: Add support to get cr50 firmware version
......................................................................
drivers/i2c/tpm/cr50: Add support to get cr50 firmware version
cr50-based devices that use the I2C protocol may still need to know
the firmware version of the cr50, therefore port this functionality
from the SPI driver to I2C.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Change subject: drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
......................................................................
drivers/i2c/tpm/cr50: Add support to get and set BOARD_CFG register
The cr50 BOARD_CFG register has a bit to support extended interrupt
pulses to the PCH. There is support for this in the SPI driver, but
not in the I2C driver, and it may be required for some boards,
therefore port the logic over to the I2C driver.
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Change subject: src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
......................................................................
src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
There may be occasions where an I2C device was initialized during
"early initialization," but when used again in ENV_PAYLOAD_LOADER
before resource allocation happens, it would currently return that it
has not been assigned a BAR. However, because of the early BAR
assigned to it, it should still be valid to use that until proper
resources have been assigned, therefore return any BAR that may have
been assigned to the device during early initialization.
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