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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61719 )
Change subject: src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
......................................................................
src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
There may be occasions where an I2C device was initialized during
"early initialization," but when used again in ENV_PAYLOAD_LOADER
before resource allocation happens, it would currently return that it
has not been assigned a BAR. However, because of the early BAR
assigned to it, it should still be valid to use that until proper
resources have been assigned, therefore return any BAR that may have
been assigned to the device during early initialization.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6
---
M src/soc/intel/common/block/i2c/i2c.c
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61719/1
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 7fdf818..acfb053 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -127,7 +127,12 @@
if (res)
return res->base;
- return (uintptr_t)NULL;
+ /* No resource found yet, it's possible this is running in the
+ * PAYLOAD_LOADER stage before resources have been assigned yet,
+ * therefore, any early init BAR should still be valid. */
+
+ /* Read the first base address for this device */
+ return (uintptr_t)ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
}
/*
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/efs_fmap_check.c
3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61558/2
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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 18:
(1 comment)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/b4643cac_64aaab6d
PS17, Line 26: memory base offset from PCI offset 0x18 value
> can you please help to write the help text better to make it relevant in several years from now.
Done
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Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
soc/intel/graphics: Create Kconfig for mapping graphic memory base
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/18
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 4:
(1 comment)
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/c6b94638_5eef3f3a
PS4, Line 336: "Reserved",
> Then, maybe these are GPP_U0, GPP_U1, GPP_U2 and GPP_U3? Possibly undocumented.
Yes, they are. Usually there's a bunch of pins marked RSVD in the PCH DS (until Cometlake, EDS after). Some of them might be connected to some of the reserved pads, or maybe the reserved pads are really NC internally. Only Intel knows... :/
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table after normalizing to the zero-point value. Although
consumer CSE sku also supports this feature, it was validated on
CSE Lite sku only.
BUG=b:182575295
TEST=Able to see TS elapse prior to IA reset on Brya/Redrix
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 88,000
945:CSE started to handle ICC configuration 88,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000)
0:1st timestamp 330,857 (48,857)
11:start of bootblock 341,811 (10,953)
12:end of bootblock 349,299 (7,487)
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/telemetry.c
M src/soc/intel/common/block/include/intelblocks/cse.h
5 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59507/16
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