Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Felix Held.
Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61559 )
Change subject: soc/amd/sabrina: Move EFS into FMAP section
......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61559/comment/5ef90622_d8132454
PS1, Line 7: Moving
> Please use imperative mood: Move ….
done
https://review.coreboot.org/c/coreboot/+/61559/comment/20f42ede_34580e70
PS1, Line 9: The chausie mainboard uses the first 128kByte of SPI flash for the EC
: firmware.
> And this conflicts with EFS?
Added more details in the commit message. If the EC uses the entire first 128kB of flash, there is no room to fit the EFS inside a CBFS that starts at 128kB. The EFS is moved out of CBFS using FMAP so that it can be located at the 128kB offset it wants to be at.
Patchset:
PS1:
> i'd split this patch into a soc code change and a board code change on top of the soc code patch
done
PS1:
> you'll also need to change the chromeos fmd file in order for the build test to pass; that is the on […]
changed the config to not enable this on chromeos
Patchset:
PS2:
Updates per comments
File src/mainboard/amd/chausie/board.fmd:
https://review.coreboot.org/c/coreboot/+/61559/comment/ad48ae2b_d6e0cd9f
PS1, Line 4: 3M
> Just FYI, we won't be able to use this on ChromeOS. The EFS header needs to be in the RO section.
In the next patch, I set it so that this option is not enabled for ChromeOS
--
To view, visit https://review.coreboot.org/c/coreboot/+/61559
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifa9333f4097705a5c572756ac3ead3ae7a0b22a4
Gerrit-Change-Number: 61559
Gerrit-PatchSet: 2
Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Tue, 08 Feb 2022 19:20:31 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org>
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: comment
Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61717 )
Change subject: mb/amd/chausie: Move EFS into FMAP section
......................................................................
mb/amd/chausie: Move EFS into FMAP section
The chausie mainboard uses the first 128kByte of SPI flash for the EC
firmware. The EFS/amdfw should be placed at the 128kByte offset. Due to
this, there is no room for the CBFS headers. The
AMD_SOC_SEPARATE_EFS_SECTION option is used to locate the EFS/amdfw via
FMAP outside of the main CBFS, and move the CBFS to a later location.
This patch enables AMD_SOC_SEPARATE_EFS_SECTION for chausie mainboards.
Change-Id: I8b5bddef199f5082bc5b541ef39a668160e9afff
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/mainboard/amd/chausie/Kconfig
M src/mainboard/amd/chausie/board.fmd
2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61717/1
diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig
index dc6e090..873d73f 100644
--- a/src/mainboard/amd/chausie/Kconfig
+++ b/src/mainboard/amd/chausie/Kconfig
@@ -10,6 +10,7 @@
select SOC_AMD_COMMON_BLOCK_USE_ESPI
select AMD_SOC_CONSOLE_UART
select MAINBOARD_HAS_CHROMEOS
+ select AMD_SOC_SEPARATE_EFS_SECTION if !CHROMEOS
config FMDFILE
default "src/mainboard/amd/chausie/chromeos.fmd" if CHROMEOS
@@ -24,7 +25,7 @@
config AMD_FWM_POSITION_INDEX
int
default 3 if CHROMEOS
- default 4
+ default 5
help
TODO: might need to be adapted for better placement of files in cbfs
diff --git a/src/mainboard/amd/chausie/board.fmd b/src/mainboard/amd/chausie/board.fmd
index 442d80f..3475c41 100644
--- a/src/mainboard/amd/chausie/board.fmd
+++ b/src/mainboard/amd/chausie/board.fmd
@@ -1,6 +1,7 @@
FLASH@0xFF000000 16M {
BIOS {
EC 128K
+ EFS 3M
RW_MRC_CACHE 64K
FMAP 4K
COREBOOT(CBFS)
--
To view, visit https://review.coreboot.org/c/coreboot/+/61717
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8b5bddef199f5082bc5b541ef39a668160e9afff
Gerrit-Change-Number: 61717
Gerrit-PatchSet: 1
Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-MessageType: newchange
Attention is currently required from: Andrey Petrov, Patrick Rudolph.
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61713
to look at the new patch set (#3).
Change subject: soc/apollolake: Correct SMBus interrupt
......................................................................
soc/apollolake: Correct SMBus interrupt
This solved the error:
i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A
i801_smbus 0000:00:1f.1: PCI INT A: not connected
i801_smbus 0000:00:1f.1: SPD Write Disable is set
i801_smbus 0000:00:1f.1: SMBus using polling
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5
---
M src/soc/intel/apollolake/acpi/pci_irqs.asl
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/61713/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/61713
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5
Gerrit-Change-Number: 61713
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger.
Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61559
to look at the new patch set (#2).
Change subject: soc/amd/sabrina: Move EFS into FMAP section
......................................................................
soc/amd/sabrina: Move EFS into FMAP section
The chausie mainboard uses the first 128kByte of SPI flash for the EC
firmware. The EFS/amdfw should be placed at the 128kByte offset. Due to
this, there is no room for the CBFS headers. The
AMD_SOC_SEPARATE_EFS_SECTION option is used to locate the EFS/amdfw via
FMAP outside of the main CBFS, and move the CBFS to a later location.
This patch adds support of AMD_SOC_SEPARATE_EFS_SECTION to sabrina
Change-Id: Ifa9333f4097705a5c572756ac3ead3ae7a0b22a4
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/sabrina/Makefile.inc
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61559/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/61559
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifa9333f4097705a5c572756ac3ead3ae7a0b22a4
Gerrit-Change-Number: 61559
Gerrit-PatchSet: 2
Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Won Chung, Benson Leung, Prashant Malani.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61571 )
Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants
......................................................................
Patch Set 6: Code-Review+2
(2 comments)
Patchset:
PS3:
> Hi Nick, thank you for review. […]
I don't know that a hw engineer is necessary, it sounds like your process was good.
Patchset:
PS6:
> Exactly this is in my TODO list, I will pick this up as soon as this CL lands.
Good suggestion.
--
To view, visit https://review.coreboot.org/c/coreboot/+/61571
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51
Gerrit-Change-Number: 61571
Gerrit-PatchSet: 6
Gerrit-Owner: Won Chung <wonchung(a)google.com>
Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Chen Wisley <wisley.chen(a)quantatw.com>
Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Won Chung <wonchung(a)google.com>
Gerrit-Attention: Benson Leung <bleung(a)chromium.org>
Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org>
Gerrit-Comment-Date: Tue, 08 Feb 2022 19:03:17 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Comment-In-Reply-To: Won Chung <wonchung(a)google.com>
Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/7c2508b8_7c0338cf
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH?? seriously?! A Kconfig option that says coreboot runs its own code before launching a payload?? Sorry but that is just ridiculous. Coreboot integrates FSP and not the other way around so there should be no flags to indicate that coreboot runs it's own code rather than FSP.
>
> I would even argue to reverse the current flags: let the FSP code conditionally run with CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE & CONFIG_USE_FSP_NOTIFY_READY_TO_BOOT and skip the native code when those are selected. This is consistent with CONFIG_USE_INTEL_FSP_MP_INIT, where using coreboot MP init is also default.
Dropping `SKIP_` is nice feedback, I know that I had introduced it few weeks back but I totally agree with the intention and logic that Arthur mentioned here. I will do then needful.
--
To view, visit https://review.coreboot.org/c/coreboot/+/60405
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
Gerrit-Change-Number: 60405
Gerrit-PatchSet: 25
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Comment-Date: Tue, 08 Feb 2022 18:58:23 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>
Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/e8383f03_92a534d1
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> Yeah agreed with Subrata here - current naming conventions are aligned to FSP API calls, just simple […]
CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH?? seriously?! A Kconfig option that says coreboot runs its own code before launching a payload?? Sorry but that is just ridiculous. Coreboot integrates FSP and not the other way around so there should be no flags to indicate that coreboot runs it's own code rather than FSP.
I would even argue to reverse the current flags: let the FSP code conditionally run with CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE & CONFIG_USE_FSP_NOTIFY_READY_TO_BOOT and skip the native code when those are selected. This is consistent with CONFIG_USE_INTEL_FSP_MP_INIT, where using coreboot MP init is also default.
--
To view, visit https://review.coreboot.org/c/coreboot/+/60405
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
Gerrit-Change-Number: 60405
Gerrit-PatchSet: 25
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Comment-Date: Tue, 08 Feb 2022 18:50:54 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-MessageType: comment
Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )
Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
Patch Set 14: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/61520
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
Gerrit-Change-Number: 61520
Gerrit-PatchSet: 14
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Comment-Date: Tue, 08 Feb 2022 18:36:20 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment