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Change subject: soc/qualcomm/common: Add dram information to CBMEM table
......................................................................
soc/qualcomm/common: Add dram information to CBMEM table
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
---
M src/soc/qualcomm/common/include/soc/qclib_common.h
M src/soc/qualcomm/common/qclib.c
2 files changed, 35 insertions(+), 0 deletions(-)
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Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
libpayload: Parse DDR Information through coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
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---
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A src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
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Change subject: src/lib: Add CBMEM tag id to parse ddr information
......................................................................
src/lib: Add CBMEM tag id to parse ddr information
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f
---
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 )
Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 17: Code-Review+1
(1 comment)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/83f807d6_5b142f5b
PS17, Line 26: memory base offset from PCI offset 0x18 value
can you please help to write the help text better to make it relevant in several years from now.
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Change subject: soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/pci/amd_pci_mmconf.c:
https://review.coreboot.org/c/coreboot/+/61680/comment/a4b98e42_23d7dceb
PS1, Line 15: CONFIG_ECAM_MMCONF_BASE_ADDRESS
> i've verified that the kconfig values can be bigger than 32 bits. […]
I wonder if the number is getting truncated since it's missing the ULL suffix.
If you do a
```
uint64_t val = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
printk(BIOS_ERR, "%llx\n", val);
```
with a 64 bit number does it actually print it out correctly, or is it truncated?
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61681 )
Change subject: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO
......................................................................
soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to
configure the PCI MMCONF base address.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681
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---
M src/soc/amd/sabrina/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 43c96c0..239a0e8 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -59,7 +59,7 @@
select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
- select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61680 )
Change subject: soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/pci/amd_pci_mmconf.c:
https://review.coreboot.org/c/coreboot/+/61680/comment/c21b75e3_f3ab5bac
PS1, Line 15: CONFIG_ECAM_MMCONF_BASE_ADDRESS
> Is it even possible for this #define to contain a 64 bit number? Doesn't the constant need the LL su […]
i've verified that the kconfig values can be bigger than 32 bits. when it's a 32 bit number, i however got a build failure without the cast
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