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Change subject: soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/stb.c:
PS3:
> since this is likely common code, it would be good to move it to soc/amd/common/block/stb
ok, this seems to contain cezanne-specific parts
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Change subject: soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/cezanne/stb.c:
PS3:
since this is likely common code, it would be good to move it to soc/amd/common/block/stb
https://review.coreboot.org/c/coreboot/+/61690/comment/cb6c8193_b66ee5fd
PS3, Line 9: #define AMD_PMC_STB_INDEX_ADDRESS 0xF8
: #define AMD_PMC_STB_INDEX_DATA 0xFC
hmm. can we use the existing smn read and write functions instead?
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Change subject: soc/intel/common: Add crashlog SRAM PCI device IDs for TGL-U/Y and ADL-P
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
@Tim, can you please rebase this CL as first patch in this trend and address the open comments? I think we can get rid of this one ?
Or you want me to address this ?
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Change subject: soc/intel/crashlog: Temporarily remove to reorganize
......................................................................
Patch Set 1: Code-Review+2
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Change subject: console/post: Lower post code loglevel to BIOS_INFO
......................................................................
Patch Set 1:
(1 comment)
File src/console/post.c:
https://review.coreboot.org/c/coreboot/+/61692/comment/e479312a_6c22ed0b
PS1, Line 22: BIOS_NOTICE
commit message says BIOS_INFO.
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Change subject: mb/google/reef: Add VBTs for all variants
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/reef/variants/coral/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61685/comment/ad22fee6_3aba5e34
PS1, Line 14: $(call add_vbt_to_cbfs, vbt-santa.bin, santa-data.vbt)
> It's *HAVE*_VBT that should be selected, right? AIUI, without guards, the user's […]
yes sorry, INTEL_GMA_HAVE_VBT is selected (and not user deselectable).
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Hello build bot (Jenkins), Michał Kopeć, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52781
to look at the new patch set (#11).
Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
......................................................................
cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
Create the correct MTRR solution based on the physical address space
provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not
account for lost C6 DRAM storage MTRR during postcar frame creation.
The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and
overlapping with usable DRAM WB MTRR. However this UC MTRR remained on
APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR
function to create correct MTRR solution that propagates to APs. This
also fixes the inconsistent MTRRs warning.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
1 file changed, 30 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/11
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61714 )
Change subject: libpayload/libc/coreboot: Fix CBFS MCache size
......................................................................
Patch Set 1: Code-Review+1
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Igor Bagnucki has uploaded a new patch set (#17) to the change originally created by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/57078 )
Change subject: src/cpu/power9: add file structure for power9, implement SCOM access
......................................................................
src/cpu/power9: add file structure for power9, implement SCOM access
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015
Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/arch/ppc64/include/arch/byteorder.h
M src/arch/ppc64/include/arch/io.h
M src/cpu/Makefile.inc
A src/cpu/power9/Kconfig
A src/cpu/power9/Makefile.inc
A src/cpu/power9/power9.c
A src/cpu/power9/scom.c
A src/include/cpu/power/scom.h
A src/include/cpu/power/spr.h
9 files changed, 414 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/57078/17
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