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Change subject: mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
......................................................................
Patch Set 10: Code-Review+2
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Hello build bot (Jenkins), Anil Kumar K, Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
......................................................................
mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/10
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
......................................................................
soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension to existing macro USB2_PORT_MAX.
The change is required to enable port reset event on a USB2 port.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state.
BUG=b:193287279
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
---
M src/soc/intel/alderlake/include/soc/usb.h
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61623/5
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61637 )
Change subject: soc/mediatek/mt8173/dramc_pi_calibration_api.c: Remove duplicated "ERROR" in log message
......................................................................
Patch Set 1:
(1 comment)
File src/soc/mediatek/mt8173/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/61637/comment/b6362208_40010652
PS1, Line 594: error
nit: what about changing this to
Error at bit %d
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
......................................................................
soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension to existing macro USB2_PORT_MAX.
The change is required to enable port reset event on a USB2 port.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state.
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
---
M src/soc/intel/alderlake/include/soc/usb.h
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61623/4
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
......................................................................
mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/9
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Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61547 )
Change subject: vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> I still can't find emmc-related parameters in FspsUpd.h.
I am working on this with internal teams. will push in next revision. mean while let's merge this so coreboot build is unblocked.
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