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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
Patch Set 47:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/56773/comment/a7c7b758_55c65edc
PS46, Line 234: AMD_FW_PSP_TRUSTLETKEY
> AMD_FW_PSP_RECOVERY: not for A/B reocvery for sure. […]
Done.
For the FW entry AMD_FW_PSP_TRUSTLETKEY, it was in PSP directory and now it is in BIOS table. For the new APU, we dont need to set the flag for AB.
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Change subject: payloads/tianocore: Rework Makefile
......................................................................
Patch Set 23:
(1 comment)
File payloads/external/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61620/comment/c31e2dc9_b092413f
PS23, Line 139: ${CONFIG_PAYLOAD_FILE}
This seems to break it (no rule to make "build/UEFIPAYLOAD.fd") - did I miss something?
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Change subject: mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/usb.h:
https://review.coreboot.org/c/coreboot/+/61586/comment/963ec90a_6674859b
PS7, Line 97: /* Type-C Port, Max TX and Pre-emp settings */
> Can we move all macro related changes in single patch here: https://review.coreboot. […]
Ack
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Hello build bot (Jenkins), Anil Kumar K, Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
......................................................................
mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port mapped to Type-C and sets Max
TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/8
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
......................................................................
soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension existing macro USB2_PORT_MAX
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TEST=Build the code for Gimble board
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---
M src/soc/intel/alderlake/include/soc/usb.h
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61623/3
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Change subject: TEST-ONLY: Refactor dramc_param to common header
......................................................................
Patch Set 4:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61293/comment/42652f31_83e56673
PS4, Line 7: Refactor dramc_param
Move ddr_base_info
(I assume this is for ddr_base_info, right?)
https://review.coreboot.org/c/coreboot/+/61293/comment/5c99897e_216040f1
PS4, Line 9: The file dramc_param.h on different platform(8192/8195/8186)
: share many the same structures. Also, adding a new member on
: one platform may cause the other build error and runtime
: error because they share the common memory.c. To avoiding
: this bad condition, reuse dramc_param as much as possible.
The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To decrease duplicate code, move it as well as other related structs and enums to a common header.
Patchset:
PS4:
I think we can merge this even without the CB:61334.
So I'll start reviewing, and please rebase! Thanks.
File src/soc/mediatek/common/include/soc/dramc_param_common.h:
https://review.coreboot.org/c/coreboot/+/61293/comment/4e3ef93e_d3854684
PS4, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> DOS line endings
Please fix.
File src/soc/mediatek/mt8186/include/soc/dramc_param.h:
https://review.coreboot.org/c/coreboot/+/61293/comment/e51b6d08_c940c812
PS4, Line 14: #include <soc/dramc_param_common.h>
This doesn't need to be changed. The original order is correct.
File src/soc/mediatek/mt8192/include/soc/dramc_param.h:
https://review.coreboot.org/c/coreboot/+/61293/comment/fa0d8af7_3d51e45a
PS4, Line 125: struct dramc_data {
: struct ddr_base_info ddr_info;
: struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
: };
:
: struct dramc_param {
: struct dramc_param_header header;
: void (*do_putc)(unsigned char c);
: struct dramc_data dramc_datas;
: };
:
Did you remove this intentionally?
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Change subject: TEST-ONLY: Refactor dramc_param to common header
......................................................................
Patch Set 4: -Code-Review
(1 comment)
Patchset:
PS4:
> They are different, this patch moves other non-platform structures in dramc_param.h to common.
Ah, my bad. I thought they are the same.
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Change subject: TEST-ONLY: Refactor dramc_param to common header
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Duplicate of CB:61132. Please abandon.
They are different, this patch moves other non-platform structures in dramc_param.h to common.
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Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/include/soc/usb.h:
https://review.coreboot.org/c/coreboot/+/61586/comment/681a6fd7_96e6c26b
PS7, Line 97: /* Type-C Port, Max TX and Pre-emp settings */
Can we move all macro related changes in single patch here: https://review.coreboot.org/c/coreboot/+/61623/2?
It'll be easy to differentiate between soc and mainboard changes.
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