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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61655
to look at the new patch set (#7).
Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro
......................................................................
soc/intel/common/gpio: Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro
Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro to support mainboard
to lock NC and GPI_SCI pins as applicable.
BUG=b:216583542
TEST=build passed
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61655/7
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Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support
......................................................................
Abandoned
merged with CB:61655
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Change subject: util/ifdtool: add PLATFORM_IFD2 to reduce common ifd tool change
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> +1 but why not replacing all platform listen here as well https://review.coreboot. […]
Understood the dependency of having more reason why we need name quirk instead generic
what i would recommend now
1. Don't remove ADL and TGL macros as there is not much advantage of doing such
2. Keep new macro ifdv2 for internal soc development purpose alone and add correct name when u r ready for upstream
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Change subject: [TESTME] soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUS
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55430/comment/64225c07_06c7f2b4
PS5, Line 10: talk to each other via PCI, there is no longer the requirement that the
> oh, the spec says system bus vs (legacy) apic bus; not sure where i got the pci from
PCI might be the more accurate terminology in the sense IOAPIC acts as the initiator for a memory write, and might be gated with the PCI_COMMAND BUSMASTER bit. IOMMU might come in to play too there.
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Change subject: mb/google/dedede/var/pirika: Add Wifi SAR for pasara
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Change subject: util/ifdtool: add PLATFORM_IFD2 to reduce common ifd tool change
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+1 but why not replacing all platform listen here as well https://review.coreboot.org/c/coreboot/+/61576/4/util/ifdtool/ifdtool.c#251
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Change subject: mb/google/var/volmar: Add gpios to lock
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Patch Set 1: Code-Review+2
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Change subject: mb/google/var/vell: Add gpios to lock
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