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Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/61672/comment/dde4c501_9417cea3
PS2, Line 444: PAD_LOCK(lock_action))
> Yes
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#18).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 84 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/18
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61672 )
Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/61672/comment/d1998b4d_11d32d56
PS2, Line 444: PAD_LOCK(lock_action))
> you mean move up?
Yes
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61623 )
Change subject: soc/intel/alderlake: Define USB2_PORT_MAX macro
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
PS1:
> Why not add a new macro?
There are no consumers for old macro USB2_PORT_MAX, hence I have removed it.
https://review.coreboot.org/c/coreboot/+/61623/comment/ce01e648_3c21ea24
PS1, Line 7: soc/intel/alderlake: Update USB2_PORT_MAX macro
> Maybe: […]
Ack
https://review.coreboot.org/c/coreboot/+/61623/comment/cda3ae23_d3c02b5d
PS1, Line 9: USB2_PORT_MAX
> Can USB 2 have Type-C?
No, USB2 port lines can be mapped to Type-C.
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Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/61672/comment/d9d41717_56bda35f
PS2, Line 444: PAD_LOCK(lock_action))
> nit: fits on previous line
you mean move up?
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Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/61672/comment/2b2d6bd2_2606b948
PS2, Line 444: PAD_LOCK(lock_action))
nit: fits on previous line
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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/net/r8168.c:
https://review.coreboot.org/c/coreboot/+/61267/comment/ee966e37_19b0ff97
PS3, Line 359: /* Enable ASPM_L1.2 */
: if (CONFIG(PCIEXP_ASPM))
: enable_aspm_l1_2(io_base);
> Basically, yes. The solutions will also work for 8168. […]
I see, thank you for the explanation. Since the Kconfig is supposed to be a global enable, how about we bring back the devicetree option and then make this conditional look like
```
if (CONFIG(PCIEXP_ASPM) && config->enable_aspm)
enable_aspm_l1_2(io_base);
```
?
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Change subject: mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 2: Code-Review+1
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS
......................................................................
mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS
use DEV_PTR to get codec HID for simplify the variant.c code
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38
---
M src/mainboard/google/volteer/variants/delbin/overridetree.cb
M src/mainboard/google/volteer/variants/delbin/variant.c
2 files changed, 5 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/61671/2
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VS
......................................................................
mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753
---
M src/mainboard/google/volteer/variants/copano/Makefile.inc
M src/mainboard/google/volteer/variants/copano/overridetree.cb
A src/mainboard/google/volteer/variants/copano/variant.c
3 files changed, 33 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/61674/2
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