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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61675
to look at the new patch set (#2).
Change subject: mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VS
......................................................................
mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30
---
M src/mainboard/google/volteer/variants/drobit/Makefile.inc
M src/mainboard/google/volteer/variants/drobit/overridetree.cb
A src/mainboard/google/volteer/variants/drobit/variant.c
3 files changed, 33 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/61675/2
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Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59507 )
Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/59507/comment/b1eeaa88_8645a57b
PS15, Line 160: if (CONFIG(SOC_INTEL_CSE_PRE_CPU_TELEMETRY))
: cse_get_telemetry_data();
> Can you move the code to line#153?
Thanks, I will check that.
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/59507/comment/e2e81396_c15207d9
PS15, Line 160: if (CONFIG(SOC_INTEL_CSE_PRE_CPU_TELEMETRY))
: cse_get_telemetry_data();
Can you move the code to line#153?
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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 )
Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
Patch Set 11:
(1 comment)
File src/soc/amd/common/block/psp/psb.c:
https://review.coreboot.org/c/coreboot/+/60968/comment/00cb43bb_b6a00b8c
PS11, Line 133: static enum cb_err psb_get_hsti_status(uint32_t *status)
> this basically does the same as https://review.coreboot. […]
Will use psb_get_hsti_status from PR:61462 once checked-in.
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Frank Chu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61700 )
Change subject: mb/google/dedede/var/pirika: Add Wifi SAR for convertibles
......................................................................
Abandoned
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Hello Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Define USB2_PORT_MAX macro
......................................................................
soc/intel/alderlake: Define USB2_PORT_MAX macro
The patch defines USB2_PORT_MAX macro. The macro USB2_PORT_MAX sets
Max TX and Pre-emp settings for the specified USB2 port.
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
---
M src/soc/intel/alderlake/include/soc/usb.h
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61623/2
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Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61267 )
Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/net/r8168.c:
https://review.coreboot.org/c/coreboot/+/61267/comment/0adcff52_05282013
PS3, Line 359: /* Enable ASPM_L1.2 */
: if (CONFIG(PCIEXP_ASPM))
: enable_aspm_l1_2(io_base);
> Is this applicable to both the 8168 and 8125 ?
Basically, yes. The solutions will also work for 8168. However for example the project Puff, which has set the "stop_gpio" in devicetree, we have to remove that code first or this solution would fail. If we cannot do that, the previous patchset which using "enable_aspm=1" in devicetree would be better?
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