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Hello Reka Norman,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61694
to review the following change.
Change subject: mb/google/brya/var/nivviks: Implement WWAN power sequencing
......................................................................
mb/google/brya/var/nivviks: Implement WWAN power sequencing
Nissa is using the FM101, which has the following power sequencing
requirements:
Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L
Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN
Add a power resource to the USB device, and use wwan_power.asl to
handle the power off sequence.
BUG=b:217092522
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
3 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61694/1
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 7613730..935d2e9 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -85,6 +85,7 @@
bool "-> Nivviks"
select BOARD_GOOGLE_BASEBOARD_NISSA
select DRIVERS_INTEL_MIPI_CAMERA
+ select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_NEREID
bool "-> Nereid"
diff --git a/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h b/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h
index c4fe342..c96b01f 100644
--- a/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h
@@ -5,4 +5,8 @@
#include <baseboard/gpio.h>
+#define WWAN_FCPO GPP_D6
+#define WWAN_RST GPP_F12
+#define T2_OFF_MS 20
+
#endif
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index 646dcb1..397025b 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -281,6 +281,11 @@
chip drivers/usb/acpi
register "desc" = ""USB2 WWAN""
register "type" = "UPC_TYPE_INTERNAL"
+ register "has_power_resource" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)"
+ register "reset_off_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+ register "enable_delay_ms" = "20"
device ref usb2_port4 on
probe DB_USB DB_1C_LTE
end
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Hello Reka Norman,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61693
to review the following change.
Change subject: mb/google/brya: Support power sequencing for USB-only WWAN
......................................................................
mb/google/brya: Support power sequencing for USB-only WWAN
Nissa is using the FM101 which is USB only. To allow us to reuse the
existing wwan_power.asl for power sequencing, move the PCIe-specific
part behind a new Kconfig HAVE_PCIE_WWAN.
BUG=b:217092522
TEST=Build brya0 and check that generated dsdt.asl doesn't change.
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/wwan_power.asl
3 files changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/61693/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 386aa11..2628000 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -202,7 +202,11 @@
Select this if the variant has a WWAN module and requires the poweroff sequence
to be performed on shutdown. Must define WWAN_FCPO, WWAN_RST and WWAN_PERST GPIOs
in variant.h, as well as T1_OFF_MS (time between PERST & RST) and T2_OFF_MS (time
- between RST and FCPO).
+ between RST and FCPO). WWAN_PERST and T1_OFF_MS are only necessary for PCIe WWAN
+ (when HAVE_PCIE_WWAN is also selected).
+
+config HAVE_PCIE_WWAN
+ def_bool n
config USE_PM_ACPI_TIMER
default n
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 83c148f..7613730 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -13,6 +13,7 @@
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GFX_GENERIC
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_ANAHERA4ES
@@ -20,6 +21,7 @@
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GFX_GENERIC
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_BRASK
@@ -33,6 +35,7 @@
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_MIPI_CAMERA
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CRASHLOG
@@ -42,6 +45,7 @@
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_MIPI_CAMERA
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CRASHLOG
@@ -90,12 +94,14 @@
bool "-> Primus"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_PRIMUS4ES
bool "-> Primus4ES"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_REDRIX
@@ -108,6 +114,7 @@
select DRIVERS_I2C_MAX98390
select DRIVERS_INTEL_MIPI_CAMERA
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
select SOC_INTEL_COMMON_BLOCK_IPU
@@ -121,6 +128,7 @@
select DRIVERS_I2C_MAX98390
select DRIVERS_INTEL_MIPI_CAMERA
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+ select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
select SOC_INTEL_COMMON_BLOCK_IPU
diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl
index d9bb5e7..f19a5ef 100644
--- a/src/mainboard/google/brya/wwan_power.asl
+++ b/src/mainboard/google/brya/wwan_power.asl
@@ -4,8 +4,10 @@
Method (MPTS, 1)
{
+#if CONFIG(HAVE_PCIE_WWAN)
\_SB.PCI0.CTXS(WWAN_PERST);
Sleep(T1_OFF_MS)
+#endif
\_SB.PCI0.CTXS(WWAN_RST);
Sleep(T2_OFF_MS)
\_SB.PCI0.CTXS(WWAN_FCPO);
--
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61692 )
Change subject: console/post: Lower post code loglevel to BIOS_INFO
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
FWIW I did some digging and this was changed from INFO to EMERG back in 2004 for no clearly documented reason, and has been like that ever since. +Ron in case he remembers a good reason why this needs to be like this, I can't see any.
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Change subject: soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/cezanne/stb.c:
https://review.coreboot.org/c/coreboot/+/61690/comment/889b840a_7a1c726b
PS3, Line 11: 0x03E30600
Is it the address where the STB resides?
https://review.coreboot.org/c/coreboot/+/61690/comment/321b61bb_e1f9b8c0
PS3, Line 30: for (i = 0; i < FIFO_SIZE; i++) {
Is it ok to stop at the STB_MARKER that we inserted instead of dumping the entire FIFO. May be it will reduce the noise.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#17).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 86 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/17
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61307 )
Change subject: console: Add ANSI escape sequences for highlighting
......................................................................
Patch Set 8:
(1 comment)
File src/commonlib/include/commonlib/loglevel.h:
https://review.coreboot.org/c/coreboot/+/61307/comment/a0eca324_05646366
PS8, Line 193: BIOS_EMERG
> lol, apparently POST codes are BIOS_EMERG so they blink. […]
Oops, yeah, I agree... uploaded CB:61692.
I was wondering if people would get bothered by the blinking anyway, it is kinda glaring. The other common case that uses BIOS_EMERG is die(), where I guess it is appropriate, but it might still be annoying to have those blink. If people don't like that I'm also fine to just reuse the same formatting for BIOS_ALERT and BIOS_EMERG (the codes above BIOS_ERR are used so rarely anyway that the differentiation isn't very important).
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Hello Raul Rangel,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61692
to review the following change.
Change subject: console/post: Lower post code loglevel to BIOS_INFO
......................................................................
console/post: Lower post code loglevel to BIOS_INFO
Post codes don't signify an emergency error, so they shouldn't be
classified as BIOS_EMERG. Now that loglevels are more visible, this
misclassification looks pretty glaring. This patch changes them to
BIOS_INFO which seems more appropriate for an informational code that is
expected to occur in the normal boot flow.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I85c8768232ae0cbf65669a7ee6abd538a3b2d5e1
---
M src/console/post.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/61692/1
diff --git a/src/console/post.c b/src/console/post.c
index 21ab000..050ed53 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -19,7 +19,7 @@
arch_post_code(value);
if (CONFIG(CONSOLE_POST))
- printk(BIOS_EMERG, "POST: 0x%02x\n", value);
+ printk(BIOS_NOTICE, "POST: 0x%02x\n", value);
mainboard_post(value);
}
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Change subject: mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UART
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/61612/comment/e7d73bef_41179012
PS1, Line 15: !CONSOLE_SERIAL
IS this needed? I see CBMEM_DUMP_TO_UART already depends on !CONSOLE_SERIAL.
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Change subject: soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS
......................................................................
Patch Set 1: Code-Review+2
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