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Change subject: mb/google/brya/var/nivviks: Add MT62F512M32D2DR-031 WT:B for P1 build
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/var/nivviks: Disable LTE-related GPIOs based on fw_config
......................................................................
Patch Set 1: Code-Review+2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61683 )
Change subject: mb/google/reef/coral: Sync mainboard.c with Chromium fork
......................................................................
Patch Set 4:
(3 comments)
File src/mainboard/google/reef/variants/coral/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140226):
https://review.coreboot.org/c/coreboot/+/61683/comment/56045be0_3c7fa296
PS4, Line 148: break;
break is not useful after a goto or return
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140226):
https://review.coreboot.org/c/coreboot/+/61683/comment/6ba0f5cc_16f0616f
PS4, Line 152: break;
break is not useful after a goto or return
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140226):
https://review.coreboot.org/c/coreboot/+/61683/comment/50c7588e_474b00bb
PS4, Line 156: break;
break is not useful after a goto or return
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Attention is currently required from: Eugene Myers.
Hello Eugene Myers,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61689
to review the following change.
Change subject: security/intel/stm: Make STM setup MP safe
......................................................................
security/intel/stm: Make STM setup MP safe
Some processor families allow for SMM setup to be done in parallel.
On processors that have this feature, the BIOS resource list becomes
unusable for some processors during STM startup.
This patch covers two cases: (1) The BIOS resource list becomes twice
as long because the smm_relocation function is called twice - this is
resolved by recreating the list on each invocation. (2) Not all
processors receive the correct resource list pointer - this is resolved
by having every processor execute the pointer calculation code, which is
a lot faster then forcing all processors to spin lock waiting for this
value to be calculated.
This patch has been tested on a Purism L1UM-1X8C and Purism 15v4.
Signed-off-by: Eugene Myers <cedarhouse(a)comcast.net>
Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37
---
M src/security/intel/stm/StmPlatformResource.c
M src/security/intel/stm/StmPlatformSmm.c
2 files changed, 11 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61689/1
diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c
index 75d52a2..4e56e2e 100644
--- a/src/security/intel/stm/StmPlatformResource.c
+++ b/src/security/intel/stm/StmPlatformResource.c
@@ -167,9 +167,14 @@
/*
* Add resources to BIOS resource database.
*/
+
+extern uint8_t *m_stm_resources_ptr;
+
void add_resources_cmd(void)
{
+ m_stm_resources_ptr = NULL;
+
add_simple_resources();
add_msr_resources();
diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c
index ef02ae3..bcf935c 100644
--- a/src/security/intel/stm/StmPlatformSmm.c
+++ b/src/security/intel/stm/StmPlatformSmm.c
@@ -155,12 +155,15 @@
return;
}
+ // This code moved here because paralled SMM set can cause
+ // some processor to receive a bad value
+ // calculate the location in SMRAM
+ addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE;
+ stm_resource_heap = (uint8_t *) addr_calc;
+
if (cpu == 0) {
// need to create the BIOS resource list once
- // first calculate the location in SMRAM
- addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE;
- stm_resource_heap = (uint8_t *) addr_calc;
printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n",
stm_resource_heap);
//setup the list
--
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Matt DeVillier has uploaded a new patch set (#4). ( https://review.coreboot.org/c/coreboot/+/61683 )
Change subject: mb/google/reef/coral: Sync mainboard.c with Chromium fork
......................................................................
mb/google/reef/coral: Sync mainboard.c with Chromium fork
Several commits were made to the Chromium coral branch
(firmware-coral-10068.B) which were not committed upstream first.
Pull them in here:
486ce56 mainboard/google/coral: Override VBT selection for babymako
c1d7720 Babymako: add touchpad i2c speed config
911d547 mainboard/google/coral: Override VBT selection for babytiger
730a5af Babytiger: add touchpad i2c speed config
724711e rabbid: add the touchpad i2c speed config
80c5d16 mainboard/google/coral: Override VBT selection for babymega
e8931a4 Babymega: add touchpad i2c speed config
These add support for additional coral sub-variants. The I2C speed config
changes were adapted to account for upstream changes not present in the
coral Chromium branch.
Change-Id: Idf2a53a351138aff310385f4026197d74ab6848b
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/reef/variants/coral/mainboard.c
1 file changed, 57 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/61683/4
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
soc/intel/skylake: Add function to clear PMCON status bits
This patch adds SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementation.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53
---
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/pmutil.c
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61650/2
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Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................
soc/intel/xeon_sp: Add function to clear PMCON status bits
This patch adds SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementation.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad
---
M src/soc/intel/xeon_sp/include/soc/pm.h
M src/soc/intel/xeon_sp/include/soc/pmc.h
M src/soc/intel/xeon_sp/pmutil.c
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61652/2
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Change subject: soc/intel/apollolake: Add function to clear PMCON status bits
......................................................................
soc/intel/apollolake: Add function to clear PMCON status bits
This patch adds SoC function to clear GEN_PMCON1 status bits to
align with other IA coreboot implementation.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe
---
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/61651/2
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