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Change subject: soc/amd/cezanne/psp_verstage: Implement get_uart_base
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/cezanne/psp_verstage: Implement get_uart_base
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/psp_verstage/uart.c:
https://review.coreboot.org/c/coreboot/+/61607/comment/b9279351_01f64cb4
PS1, Line 21: Entering verstage on PSP
> That message does not reflect the error.
lol... oops. Done
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61607
to look at the new patch set (#2).
Change subject: soc/amd/cezanne/psp_verstage: Implement get_uart_base
......................................................................
soc/amd/cezanne/psp_verstage: Implement get_uart_base
This will allow directly using the UART console. On PSP releases that
don't support mapping the UART, we will just return NULL which is
perfectly acceptable.
BUG=b:215599230
TEST=Boot guybrush and verify verstage can print to the console
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ic8d7f0fe00794a715756f92e3fb32c6b512cb8aa
---
M src/soc/amd/cezanne/psp_verstage/Makefile.inc
A src/soc/amd/cezanne/psp_verstage/uart.c
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/61607/2
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Change subject: soc/amd/common/psp_verstage: Add UART support to PSP console
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/sabrina/psp_verstage: Implement get_uart_base
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/picasso/psp_verstage: Implement get_uart_base
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/cezanne/psp_verstage: Implement get_uart_base
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/psp_verstage/uart.c:
https://review.coreboot.org/c/coreboot/+/61607/comment/b04185c3_4b79fc8a
PS1, Line 21: Entering verstage on PSP
That message does not reflect the error.
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Hello Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61690
to look at the new patch set (#3).
Change subject: soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock
......................................................................
soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock
This will make it easier to inspect the smart trace buffer. This
buffer contains POST codes and other debug data that can be useful to
understand what the system is doing.
This functionality was ported over from the linux amd-pmc driver.
BUG=b:217960752
TEST=Boot guybrush and verify STB is dumped
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ied3010ba0fc1d7327fe07df562f0483099d6b165
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/cezanne/bootblock.c
A src/soc/amd/cezanne/include/soc/stb.h
A src/soc/amd/cezanne/stb.c
5 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/61690/3
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Change subject: console: Add ANSI escape sequences for highlighting
......................................................................
Patch Set 8:
(1 comment)
File src/commonlib/include/commonlib/loglevel.h:
https://review.coreboot.org/c/coreboot/+/61307/comment/2bb87dc3_d5aae24b
PS8, Line 193: BIOS_EMERG
lol, apparently POST codes are BIOS_EMERG so they blink. Wonder if we can change those to INFO without anyone yelling.
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