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Change subject: src/lib: Add CBMEM tag id to parse ddr information
......................................................................
Patch Set 26:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59194/comment/a0709c2e_ed11629b
PS21, Line 9: BUG=b:182963902,177917361
> You acked this, but didn't make the actual change.
Done
https://review.coreboot.org/c/coreboot/+/59194/comment/f477db03_047b24a7
PS21, Line 10: developement
> same here.
Done
File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h:
https://review.coreboot.org/c/coreboot/+/59194/comment/fd812cb9_2e23f6b7
PS21, Line 157: { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}, \
> This is still here as well.
Done
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61650/comment/977516e3_7488fea3
PS2, Line 7: PMCON
> nit: Can we use consistent naming (either PMCON or GEN_PMCON_A <preferred one>)?
This is what it is documented in two different EDS. Do you think it's possible for unification at the EDS source itself?
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Change subject: sc7280: Disable fingerprint sensor feature as its not present on device
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/herobrine/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140322):
https://review.coreboot.org/c/coreboot/+/61716/comment/5ec8ebfb_20e32984
PS1, Line 111: /* Disable fingerprint sensor intialization as its not present on device */
'intialization' may be misspelled - perhaps 'initialization'?
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Change subject: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61678/comment/c10885a5_f5b39775
PS1, Line 9: Max
> max
Ack
https://review.coreboot.org/c/coreboot/+/61678/comment/3d2b3c50_edf9a740
PS1, Line 11:
> 1. Can this operating system control that mode too? […]
The Energy Efficient Turbo is remain disabled in JSL and TGL. Performance KPIs do not hit turbo frequency if this feature is enabled.
https://review.coreboot.org/c/coreboot/+/61678/comment/6d3c8d5c_5981f0d9
PS1, Line 12: intensiv
> `intensive`
Ack
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/61678/comment/ee9227d5_73171918
PS1, Line 658: * Disable the energy efficient turbo mode */
: s_cfg->EnergyEfficientTurbo = 0;
> Looks like this is just setting a bit in MSR_POWER_CTL, could this just be moved to https://review. […]
With this feature, CPU doesn't hit turbo frequency when needed. So, all performance KPIs get effected.
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 11: Verified+1
(2 comments)
File src/mainboard/google/herobrine/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140319):
https://review.coreboot.org/c/coreboot/+/61342/comment/b7182cbc_6ae69324
PS11, Line 61: if (display_init_required()) {
suspect code indent for conditional statements (8, 24)
File src/soc/qualcomm/sc7280/display/edp_ctrl.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140319):
https://review.coreboot.org/c/coreboot/+/61342/comment/4cb616f3_6fca17f9
PS11, Line 863: ret = edp_start_link_train_2(ctrl,dpcd);
space required after that ',' (ctx:VxV)
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61650/comment/659bc130_da9a4d56
PS2, Line 7: PMCON
nit: Can we use consistent naming (either PMCON or GEN_PMCON_A <preferred one>)?
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Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/55f9f8b1_1a82f9ca
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> > What if we aggregate both operations covered by SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOT […]
Hmm, I mean remove SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE, and bring entire code (covered by these 2 flags) under CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH.
>From SoC recommendation side, Ready to Boot and End of Post are event which has meaning and silicon prefer to perform some operation under specific hoods, hence, coreboot would allow the same flexibility for SoC vendor enggs to add the required code inside specific `if` clause without mixing it.
From the code perspective, both the flags are getting executed sequentially and not as two disjoint events.
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 4:
(6 comments)
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/0256ea90_ede6b086
PS4, Line 336: "Reserved",
> one too much. […]
Then, maybe these are GPP_U0, GPP_U1, GPP_U2 and GPP_U3? Possibly undocumented.
https://review.coreboot.org/c/coreboot/+/56171/comment/7c4507ad_1105b289
PS4, Line 535: 3
I think this is actually 5? GPP_C was dumping strangely and it mismatches the pad_count.
https://review.coreboot.org/c/coreboot/+/56171/comment/411f495f_a7e419c9
PS4, Line 575: tigerlake_pch_h_group_e_names
"GPP_E0/SATAXPCIE0/SATAGP0" is missing.
https://review.coreboot.org/c/coreboot/+/56171/comment/1919f955_3d3520ea
PS4, Line 753: GPP_J
GPP_K
https://review.coreboot.org/c/coreboot/+/56171/comment/e973e73b_eae468c6
PS4, Line 759: tigerlake_pch_h_group_r_names
"GPP_R0/HDA_BCLK/I2S0_SCLK/n_a/HDACPU_BCLK," "GPP_R1/HDA_SYNC/I2S0_SFRM/n_a/n_a" and "GPP_R2/HDA_SDO/I2S0_TXD/n_a/HDACPU_SDO" are missing.
I am making some guesses as to how the GPIO functions are grouped.
https://review.coreboot.org/c/coreboot/+/56171/comment/390ff272_894c1580
PS4, Line 901: tigerlake_pch_h_communities
tigerlake_pch_h_community_3 is missing.
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Change subject: mb/google/dedede/var/pirika: Add Wifi SAR for pasara
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/dedede/variants/pirika/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61705/comment/33f108c1_f1d66fb3
PS1, Line 3: $(CONFIG_FW_CONFIG)
ramstage-y since variant.c is not looking anything in FW_CONFIG.
File src/mainboard/google/dedede/variants/pirika/variant.c:
https://review.coreboot.org/c/coreboot/+/61705/comment/89f60eb6_89a48e70
PS1, Line 4: #include <fw_config.h>
Is it required?
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