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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/7cb6bc06_c37de218
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> > Hi Subrata, are you planning to change the kconfig from SKIP_ to CONFIG_USE_ as per suggested by A […]
I saw from coreboot perspective when I made my proposal, let coreboot implement SoC recommendations in it's own way in this case(coreboot native implementation) without getting into FSP. Hence I proposed new layer that can be controlled through Kconfig (and without corelating to FSP). My bad, it is not taken positively. From the comments, it seems community supports your idea, I think you can go with your proposal!
coreboot once implements any functionality (FSP alternatives like MP_INIT or FSP-T), we naturally support it, and maintain for good reasons.
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Change subject: cpu/x86/lapic: Move LAPIC configuration to MP init
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
I found that my asus p2b would hang at the seabios screen with this merged.
I posted some logs to the mailing list.
Is there anything else I can do to try to debug this?
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Change subject: Update arm-trusted-firmware submodule to upstream master
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 18:
(2 comments)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/3cb5ae52_f691587f
PS18, Line 159: if (clk_req == CLK_DISABLE || clk_req == CLK_ENABLE)
: continue;
Why do we bail early?
https://review.coreboot.org/c/coreboot/+/61259/comment/e3838398_ad9c6f70
PS18, Line 200: }
Should we also check for the case where `pci_device->enabled` and the clk requests don't match?
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61650/comment/13f7196f_0be3a913
PS2, Line 7: PMCON
> > nit: Can we use consistent naming (either PMCON or GEN_PMCON_A <preferred one>)? […]
>This is what it is documented in two different EDS. Do you think it's possible for unification at the EDS source itself?
I prefer to take what is good and help readability in this case. But, it's your choice :)
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> sure, how to verify correctness?
For now, may be mapping against the EDS?
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Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61389
to look at the new patch set (#19).
Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
soc/intel/graphics: Create Kconfig for mapping graphic memory base
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/19
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Avinash Alevoor has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 )
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 12: Code-Review+1
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