Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61724 )
Change subject: console: Add missing va_end() in wrap_interactive_printf()
......................................................................
console: Add missing va_end() in wrap_interactive_printf()
I think this doesn't do anything on most architectures, but it should
still be there just in case. Found by Coverity.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I845a784d90f65610fd1e0d751ea13e9af5b970fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61724
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/console/printk.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/console/printk.c b/src/console/printk.c
index 8db2c45..341c255 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -74,6 +74,7 @@
va_list args;
va_start(args, fmt);
vtxprintf(console_interactive_tx_byte, fmt, args, NULL);
+ va_end(args);
}
static void line_start(union log_state state)
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Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61692 )
Change subject: console/post: Lower post code loglevel to BIOS_INFO
......................................................................
console/post: Lower post code loglevel to BIOS_INFO
Post codes don't signify an emergency error, so they shouldn't be
classified as BIOS_EMERG. Now that loglevels are more visible, this
misclassification looks pretty glaring. This patch changes them to
BIOS_INFO which seems more appropriate for an informational code that is
expected to occur in the normal boot flow.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I85c8768232ae0cbf65669a7ee6abd538a3b2d5e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61692
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/console/post.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/console/post.c b/src/console/post.c
index 21ab000..1d99a2e 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -19,7 +19,7 @@
arch_post_code(value);
if (CONFIG(CONSOLE_POST))
- printk(BIOS_EMERG, "POST: 0x%02x\n", value);
+ printk(BIOS_INFO, "POST: 0x%02x\n", value);
mainboard_post(value);
}
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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 )
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 12:
(1 comment)
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/85b6e963_f7105216
PS5, Line 29: CORE_2_PSP_MSG_38_OFFSET
can we have more descriptive name PSB_HSTI_STATUS_OFFSET?
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Change subject: tests/include: Move EMPTY_WRAP() macro to tests/include/test.h
......................................................................
Patch Set 2: Code-Review+2
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61685 )
Change subject: mb/google/reef: Add VBTs for all variants
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/reef/variants/coral/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61685/comment/837c0bd5_3a402c04
PS1, Line 14: $(call add_vbt_to_cbfs, vbt-santa.bin, santa-data.vbt)
> (or maybe better, make the macro empty if not INTEL_GMA_ADD_VBT)
done - CB:61768
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61768 )
Change subject: drivers/intel/gma: Guard add_vbt_to_cbfs macro
......................................................................
drivers/intel/gma: Guard add_vbt_to_cbfs macro
Guard macro via CONFIG_INTEL_GMA_ADD_VBT, rather than guarding
each of the calls to it (most of which are currently unguarded).
Test: build google/coral w/ and w/o CONFIG_INTEL_GMA_ADD_VBT selected,
verify VBTs added (or not) to CBFS based on Kconfig selection.
Change-Id: Ic25554cb2c61b81bdb4b0987094c3558e0bbcbd8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/drivers/intel/gma/Makefile.inc
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/61768/1
diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc
index 964d13e..5588e5a 100644
--- a/src/drivers/intel/gma/Makefile.inc
+++ b/src/drivers/intel/gma/Makefile.inc
@@ -8,6 +8,7 @@
ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c
+ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y)
# add_vbt_to_cbfs, first argument is the filename in cbfs, the second one
# is the filename in the coreboot tree.
add_vbt_to_cbfs= \
@@ -15,11 +16,10 @@
$(eval $1-file := $2) \
$(eval $1-type := raw) \
$(eval $1-compression := lzma)
-
-ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y)
-$(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE)))
endif
+$(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE)))
+
ifeq ($(CONFIG_GFX_GMA),y)
$(call add-special-class,gfxinit)
--
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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 12:
(2 comments)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/61020/comment/965b1b56_19c6e8d0
PS11, Line 9: #include <soc/soc_chip.h>
> #include "chip.h" instead #include <soc/soc_chip.h> […]
Ack
https://review.coreboot.org/c/coreboot/+/61020/comment/445b1f5c_01f5e7e6
PS11, Line 152: static void wifi_dsm_ddrrfim_func3_cb(void *ptr)
> I have an idea of how this property can be better organized, I pushed a WIP patch here: https://revi […]
Ack, rebased on top of Tim's patch and did corresponding changes
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Change subject: Update intel-sec-tools submodule to upstream master
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
It seems this breaks building OCP_DELTALAKE_CBNT. I would rebase this patch and move it to the end of the patch series.
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> @Matt, can you please check if this is good with SKL platform that you have in hand?
sure, how to verify correctness?
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 16:
(2 comments)
File src/soc/intel/common/block/cse/telemetry.c:
https://review.coreboot.org/c/coreboot/+/59507/comment/1111ed9d_ec063bb7
PS16, Line 13: s64
nit:
`timestamp_get()`
returns a uint64_t, not a signed 64-bit
https://review.coreboot.org/c/coreboot/+/59507/comment/6179ed57_f433e1fa
PS16, Line 37: (s64)
why signed? could there be "negative" timestamps?
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