Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61558 )
Change subject: soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/efs_fmap_check.c
3 files changed, 18 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig
index c5ec560..7ef7e40 100644
--- a/src/soc/amd/common/block/psp/Kconfig
+++ b/src/soc/amd/common/block/psp/Kconfig
@@ -27,3 +27,11 @@
and each mainboard can choose to select an appropriate fanless or
fanned set of blobs. Ask your AMD representative whether your APU
is considered fanless.
+
+config AMD_SOC_SEPARATE_EFS_SECTION
+ bool
+ help
+ Use separate EFS FMAP section instead of putting EFS into CBFS. The
+ FMAP section must begin exactly at the location the EFS needs to be
+ placed in the flash. This option can be used to place the EFS right
+ after the 128kByte EC firmware at the beginning of the flash.
diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc
index 94dc57c..5bae663 100644
--- a/src/soc/amd/common/block/psp/Makefile.inc
+++ b/src/soc/amd/common/block/psp/Makefile.inc
@@ -6,6 +6,7 @@
smm-y += psp_smm.c
bootblock-y += psp_efs.c
+bootblock-$(CONFIG_AMD_SOC_SEPARATE_EFS_SECTION) += efs_fmap_check.c
verstage-y += psp_efs.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP
diff --git a/src/soc/amd/common/block/psp/efs_fmap_check.c b/src/soc/amd/common/block/psp/efs_fmap_check.c
new file mode 100644
index 0000000..44dfe70
--- /dev/null
+++ b/src/soc/amd/common/block/psp/efs_fmap_check.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/psp_efs.h>
+#include <assert.h>
+#include <fmap_config.h>
+#include <soc/iomap.h>
+
+_Static_assert(FMAP_SECTION_EFS_START == (FLASH_BASE_ADDR + EFS_OFFSET),
+ "FMAP EFS Offset does not match EFS Offset - check your config");
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61719 )
Change subject: src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/i2c/i2c.c:
https://review.coreboot.org/c/coreboot/+/61719/comment/31d1a755_d48aaaca
PS2, Line 135: pci_read_config32
> @Tim, what is the difference between reading from config space and `probe_resourece` ? Are not both […]
probe_resource checks against the resource_list that is assigned during resource allocation (PCI enumeration). if probe_resource returns NULL, then no resource was allocated for that or it is before PCI enumeration happens (what this is trying to solve).
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61717 )
Change subject: mb/amd/chausie: Move EFS into FMAP section
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
this is likely broken for the chromeos case, but we're not far enough for that to really matter; i'm ok with looking into that later and getting this patch in to unblock the development
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61559 )
Change subject: soc/amd/sabrina: Move EFS into FMAP section
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File src/soc/amd/sabrina/Makefile.inc:
PS4:
this can likely be factored out into soc/amd/common/block/psp/makefile.inc, but that's something for a follow up i guess
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Change subject: mb/amd/chausie: Move EFS into FMAP section
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/amd/chausie/Kconfig:
https://review.coreboot.org/c/coreboot/+/61717/comment/05dded2a_bb6f02a6
PS3, Line 28: default 5
this can be dropped since 5 is the default AMD_FWM_POSITION_INDEX for BOARD_ROMSIZE_KB_16384
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61461 )
Change subject: mb/amd/chausie: update GPIO for chausie
......................................................................
Patch Set 6:
(4 comments)
Patchset:
PS6:
only had a brief look at this patch and haven't checked with the schematics
File src/mainboard/amd/chausie/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/61461/comment/af92e7a0_9bb478b9
PS6, Line 28: /* Deassert PCIe Reset lines */
i'd put this comment in the same level of indentation as the code
https://review.coreboot.org/c/coreboot/+/61461/comment/b6184867_4222784a
PS6, Line 50: SMBUS0
this is the I2C2 SCL and not the SMBUS0 SCL, so the comment doesn't match the code. the smbus controller could also be muxed to those pins, but it isn't used here. same for the comments below
File src/mainboard/amd/chausie/gpio.c:
https://review.coreboot.org/c/coreboot/+/61461/comment/4d283c05_292e8ed9
PS6, Line 113: SMBUS0
see my comment on the other file
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61724 )
Change subject: console: Add missing va_end() in wrap_interactive_printf()
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
would be good if you could add the coverity CID for easier cross-referencing in the future; iirc i was asked to add a found-by tag that mentions the CID in such commits some time ago
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Change subject: cpu/x86/lapic: Move LAPIC configuration to MP init
......................................................................
Patch Set 8:
(2 comments)
File src/cpu/x86/lapic/lapic.c:
https://review.coreboot.org/c/coreboot/+/58387/comment/c7a6a59f_5e84b918
PS8, Line 101: if (need_lapic_init())
Ok, so asus/p2b has SMP=n, IOAPIC=n, MAX_CPUS=1, UDELAY_LAPIC=n so it previously called disable_lapic() here but does not do it anymore.
File src/cpu/x86/lapic/lapic_cpu_init.c:
https://review.coreboot.org/c/coreboot/+/58387/comment/5b970e82_9100dccd
PS8, Line 388:
Does it work with:
} else {
disable_lapic();
}
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Change subject: Update intel-microcode submodule to upstream master
......................................................................
Patch Set 1: Code-Review+1
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Change subject: Update qc_blobs submodule to upstream master
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
+Shelley FYI, I guess we should actually do this more often. It's easy to forget since we don't rely on this in the Chrome OS build flow, but for upstream it's important that whenever new patches land in the qc_blobs repo, we also remember to uprev the submodule like this so they're actually available to users.
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