coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
by Felix Held (Code Review) 10 Feb '22

10 Feb '22

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58386 ) Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > uh oh, should have verified this patch on hardware. […] cpuid_ext(0xb, 0).edx is 0 on all cores on picasso. this really shouldn't happen -- To view, visit https://review.coreboot.org/c/coreboot/+/58386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1f46fe5091ebeab6dfb4c7e151150cf495d0cb Gerrit-Change-Number: 58386 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:22:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add function to clear PMCON status bits
by Angel Pons (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Sridhar Siricilla, Lean Sheng Tan, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61650 ) Change subject: soc/intel/skylake: Add function to clear PMCON status bits ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61650/comment/82cd0cf3_a48fc04f PS2, Line 7: PMCON > >This is what it is documented in two different EDS. […] I'd leave this as-is, APL calls this register GEN_PMCON1. -- To view, visit https://review.coreboot.org/c/coreboot/+/61650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53 Gerrit-Change-Number: 61650 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in gerrit-avatars[master]: Add avatar
by Angel Pons (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Vitaly Rodionov. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/gerrit-avatars/+/61449 ) Change subject: Add avatar ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: You should be able to submit this change yourself. -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/61449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I27108afef70431e0e84d05f997ef3144af5c5930 Gerrit-Change-Number: 61449 Gerrit-PatchSet: 4 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:13:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `finalize` operation for CSE
by Angel Pons (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Sridhar Siricilla, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Add `finalize` operation for CSE ...................................................................... Patch Set 25: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 25 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:13:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
by Angel Pons (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 ) Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/61519/comment/5aecc1b6_32d043eb PS9, Line 188: static void set_cse_end_of_post(void *unused) : { : static bool eop_sent = false; : /* : * If CSE is already hidden then accessing CSE registers would be wrong and will : * receive junk, hence, return as CSE is already disabled. : */ : if (!is_cse_enabled()) { : printk(BIOS_DEBUG, "CSE is disabled, cannot send End-of-Post (EOP) message\n"); : return; : } : : if (eop_sent) { : printk(BIOS_ERR, "EOP already sent\n"); : return; : } : : set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); : : timestamp_add_now(TS_ME_BEFORE_END_OF_POST); : handle_cse_eop_result(cse_send_eop()); : timestamp_add_now(TS_ME_AFTER_END_OF_POST); : : set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); : : eop_sent = true; : } : : void cse_send_end_of_post(void) : { : return set_cse_end_of_post(NULL); : } > really minor nit, but the call to set_cSE-send_of_post with the NULL is bugging me a little, does th […] It would work, yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:12:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Skip FSP Notify APIs
by Angel Pons (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60406 ) Change subject: soc/intel/alderlake: Skip FSP Notify APIs ...................................................................... Patch Set 21: Code-Review+1 (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/60406/comment/ea704c9b_11c13662 PS21, Line 360: : config USE_COREBOOT_NATIVE_END_OF_POST_DRIVER : bool : default y : select SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT : select SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE : > I would skip this and just select the two SKIP Kconfigs Unless there's a reason to change this, I'd also drop the Kconfig. If it's meant to be overriden through site-local, I'd document it as help text. -- To view, visit https://review.coreboot.org/c/coreboot/+/60406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0198c9568de0e74053775682a44324405746389a Gerrit-Change-Number: 60406 Gerrit-PatchSet: 21 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:11:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
by Felix Held (Code Review) 10 Feb '22

10 Feb '22

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58386 ) Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: uh oh, should have verified this patch on hardware. turns out that it breaks the picasso amd soc (tested on mandolin) and possibly also the other amd socs. with just the change in the header file, something goes so wrong that it'll get us back into bootblock: Relocation complete. Invalid CPU number assigned in SMM stub: 8 coreboot-4.14-4020-gceaf959678-dirty Sat Feb 5 07:46:50 UTC 2022 bootblock starting (log level: 7)... with the changes to the .S file applied it gets stuck with this being the last 3 lines of output: CPU #1 initialized bsp_do_flight_plan done after 378 msecs. A reverting this commit made the current coreboot master boot again on mandolin, but i'm not sure if the later patches in this area have some dependency on this one -- To view, visit https://review.coreboot.org/c/coreboot/+/58386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1f46fe5091ebeab6dfb4c7e151150cf495d0cb Gerrit-Change-Number: 58386 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:11:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Load logo into BGRT table
by Sean Rhodes (Code Review) 10 Feb '22

10 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61774 ) Change subject: acpi: Load logo into BGRT table ...................................................................... acpi: Load logo into BGRT table Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ie3ed984f2254e6af286d50fc89fa91cfe5f31b2c --- A src/acpi/bgrt.c A src/include/acpi/acpi_init.h 2 files changed, 170 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/61774/1 diff --git a/src/acpi/bgrt.c b/src/acpi/bgrt.c new file mode 100644 index 0000000..04699d0 --- /dev/null +++ b/src/acpi/bgrt.c @@ -0,0 +1,113 @@ +/** @file + + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bmp.h> +#include <vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi50.h> +#include <acpi/init_lib.h> + + +// +// ACPI Boot Graphics Resource Table template +// +CONST +EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE mBootGraphicsResourceTableTemplate = { + { + EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE), + EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + // + // It is expected that these values will be updated at EntryPoint. + // + EFI_ACPI_OEM_ID, // OEM ID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM Table ID(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM Revision + EFI_ACPI_CREATOR_ID, // Creator ID + EFI_ACPI_CREATOR_REVISION // Creator Revision + }, + EFI_ACPI_5_0_BGRT_VERSION, // Version + EFI_ACPI_5_0_BGRT_STATUS_VALID, // Status + EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP, // Image Type + 0, // Image Address + 0, // Image Offset X + 0 // Image Offset Y +}; + + +/** + Update Boot Graphics Resource Table (BGRT). + + @param[in] Table Pointer of ACPI BGRT Table. + + @retval EFI_SUCCESS Update ACPI BGRT table successfully. + @retval OthersFailed to update FPDT table. + **/ +EFI_STATUS +UpdateBgrt ( + IN UINT8 *Table +) +{ + UINT32 BmpBase; + UINT32 OffX; + UINT32 OffY; + EFI_STATUS Status; + EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE *Bgrt; + EFI_PEI_GRAPHICS_INFO_HOB *GfxInfoHob; + BMP_IMAGE_HEADER *BmpHdr; + BMP_IMAGE_HEADER *OrgBmpHdr; + UINT32 ImageLen; + UINT32 FileLen; + + if (PcdGet32 (PcdSplashLogoAddress) == 0) { + return EFI_UNSUPPORTED; + } + + // Get framebuffer info + GfxInfoHob = (EFI_PEI_GRAPHICS_INFO_HOB *)GetGuidHobData (NULL, NULL, &gEfiGraphicsInfoHobGuid); + if (GfxInfoHob == NULL) { + return EFI_UNSUPPORTED; + } + + BmpBase = PCD_GET32_WITH_ADJUST (PcdSplashLogoAddress); + Status = GetBmpDisplayPos ((VOID *)(UINTN)BmpBase, &OffX, &OffY, GfxInfoHob); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + OrgBmpHdr = (BMP_IMAGE_HEADER *)(UINTN)BmpBase; + Bgrt = (EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE *)Table; + Bgrt->ImageAddress = (UINTN)OrgBmpHdr; + if (!((OrgBmpHdr->BitPerPixel == 24) || (OrgBmpHdr->BitPerPixel == 32))) { + // Need to convert the BMP image into 32bit BMP supported by BGRT + ImageLen = (UINT32)MultU64x32 (OrgBmpHdr->PixelWidth << 2, OrgBmpHdr->PixelHeight); + FileLen = sizeof(BMP_IMAGE_HEADER) + ImageLen; + BmpHdr = (BMP_IMAGE_HEADER *)AllocatePages (EFI_SIZE_TO_PAGES (FileLen)); + if (BmpHdr != NULL) { + CopyMem (BmpHdr, OrgBmpHdr, sizeof(BMP_IMAGE_HEADER)); + BmpHdr->Size = FileLen; + BmpHdr->ImageOffset = sizeof(BMP_IMAGE_HEADER); + BmpHdr->HeaderSize = sizeof(BMP_IMAGE_HEADER) - OFFSET_OF(BMP_IMAGE_HEADER, HeaderSize); + BmpHdr->BitPerPixel = 32; + BmpHdr->CompressionType = 0; + BmpHdr->ImageSize = 0; + BmpHdr->NumberOfColors = 0; + BmpHdr->ImportantColors = 0; + Status = DisplayBmpToFrameBuffer (OrgBmpHdr, &BmpHdr[1], ImageLen, GfxInfoHob); + if (!EFI_ERROR(Status)) { + Bgrt->ImageAddress = (UINTN)BmpHdr; + } + } + } + Bgrt->ImageOffsetX = OffX; + Bgrt->ImageOffsetY = OffY; + + if (!FeaturePcdGet (PcdSplashEnabled)) { + Bgrt->Status = 0; + } + + return EFI_SUCCESS; +} diff --git a/src/include/acpi/acpi_init.h b/src/include/acpi/acpi_init.h new file mode 100644 index 0000000..0df02ce --- /dev/null +++ b/src/include/acpi/acpi_init.h @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ACPI_INIT_LIB_INTERNAL_H_ +#define _ACPI_INIT_LIB_INTERNAL_H_ + + +#include <PiPei.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/AcpiInitLib.h> +#include <Library/BootloaderCoreLib.h> +#include <IndustryStandard/Acpi.h> + +#define MAX_ACPI_TEMPLATE_NUM 16 + +#define ACPI_ALIGN() (Current = (UINT8 *)ALIGN_POINTER (Current, 0x10)) +#define ACPI_ALIGN_PAGE() (Current = (UINT8 *)ALIGN_POINTER (Current, 0x1000)) + +#define EFI_ACPI_OEM_ID {'O','E','M','I','D',' '} // OEMID 6 bytes long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('O','E','M','T','A','B','L','E') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000005 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('C','R','E','A') +#define EFI_ACPI_CREATOR_REVISION 0x0100000D + +#define ACPI_SKIP 0 +#define ACPI_APPEND 1 +#define ACPI_REPLACE 2 + +extern UINT32 WakeUpBuffer; +extern CHAR8 WakeUp; +extern UINT32 WakeUpSize; + +extern CONST EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE mBootGraphicsResourceTableTemplate; + +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_MADT_ENTRY_COMMON_HEADER; + +/** + Update Boot Graphics Resource Table (BGRT). + + @param[in] Table Pointer of ACPI BGRT Table. + + @retval EFI_SUCCESS Update ACPI BGRT table successfully. + @retval OthersFailed to update FPDT table. + **/ +EFI_STATUS UpdateBgrt (IN UINT8 *Table); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/61774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ed984f2254e6af286d50fc89fa91cfe5f31b2c Gerrit-Change-Number: 61774 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brask: Enable ASPM of RTL8125
by Tim Wawrzynczak (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Rory Liu, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61268 ) Change subject: mb/google/brya/var/brask: Enable ASPM of RTL8125 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80 Gerrit-Change-Number: 61268 Gerrit-PatchSet: 4 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:05:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features
by Tim Wawrzynczak (Code Review) 10 Feb '22

10 Feb '22

Attention is currently required from: Reka Norman, Nick Vaccaro, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61730 ) Change subject: util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Gerrit-Change-Number: 61730 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 09 Feb 2022 21:04:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2022