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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#20).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 112 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/20
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 )
Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 19:
(2 comments)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/8ec6f97c_88f16a58
PS19, Line 26: to
: reach at DSM
Unless the hardware changed significantly, it's up to the graphics driver
if this points to DSM or not. Also, at what offset.
It would really be nice if somebody finds documentation about what changed
actually. graphics_get_memory_base() is not even supposed to point to DSM.
It's just the base of the logical graphics memory aperture. If the latter
is at an offset in future hardware, I can't tell. So the question boils down
to: Did the whole aperture move or did the mapping of the framebuffer
inside the aperture move (when using the FSP-integrated GOP)?
If it's just the framebuffer allocation that moved when using the
FSP-integrated GOP driver, that should be handled in the caller of
graphics_get_memory_base() and not inside the latter. Also, in case
it's about the framebuffer, a proper implementation should use
EFI_PEI_GRAPHICS_INFO_HOB and not try to guess things from register
values. However, FSP spec notes that the value may need to be updated
in case the BAR moves (e.g. via coreboot's allocator). Um, might be
easier to not use the FSP/GOP in the first place ;)
https://review.coreboot.org/c/coreboot/+/61389/comment/5c34baf8_58c3e08e
PS19, Line 29: GTT_SIZE
> So if I understand correctly, really, all this is saying is that the framebuffer that the GFX PEIM c […]
DSM used to mean the space of system DRAM that is pre-allocated for graphics,
aka. graphics stolen memory. It's where any pre-OS driver usually sets up
the framebuffer. Unless they completely changed the hardware, the space behind
BAR2 is just logical graphics memory and can point to anything via page
tables (gGTT), so it seems likely we are dealing with a software and not
a hardware change here.
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 )
Change subject: drivers: spi_flash: Addressing mode change for SPI NOR
......................................................................
Patch Set 113:
(5 comments)
File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/50586/comment/62fa7dd1_0aba6697
PS113, Line 169: This will send an Exit 4-Byte Address Mode (E9h) command before the first
> trailing whitespace
Please fix.
https://review.coreboot.org/c/coreboot/+/50586/comment/ba75a42b_06751d05
PS113, Line 170: access to the SPI flash. On some platforms with SPI flashes larger than 32MB,
> trailing whitespace
Please fix.
https://review.coreboot.org/c/coreboot/+/50586/comment/9f249a47_39a7ae33
PS113, Line 171: the SPI flash may power up in 4-byte addressing mode and this command needs
> trailing whitespace
Please fix.
https://review.coreboot.org/c/coreboot/+/50586/comment/2a9dcde0_45e6d4a3
PS113, Line 172: to be sent before coreboot's 3-byte address commands can be interpreted correctly.
> trailing whitespace
Please fix.
https://review.coreboot.org/c/coreboot/+/50586/comment/f19c8587_8fba652d
PS113, Line 173: On flashes that don't support 4-byte addressing mode or where it is already
> trailing whitespace
Please fix.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61628 )
Change subject: mb/google/brya: Mark the WWAN device as an UntrustedDevice
......................................................................
mb/google/brya: Mark the WWAN device as an UntrustedDevice
The ChromiumOS kernel has the ability to restrict devices to their own
IOMMU security domains when ACPI passes this property to a device
downstream of a PCIe RP.
BUG=b:215424986
TEST=verified the property is found and WWAN is restricted to its own
IOMMU domain as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61628
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
2 files changed, 5 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 386aa11..b398386 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -14,6 +14,7 @@
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_INTEL_USB4_RETIMER
+ select DRIVERS_PCIE_GENERIC
select DRIVERS_SOUNDWIRE_ALC5682
select DRIVERS_SOUNDWIRE_MAX98373
select DRIVERS_SPI_ACPI
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index a277120..0c0e8c4 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -166,6 +166,10 @@
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
+ chip drivers/pcie/generic
+ register "is_untrusted" = "1"
+ device pci 0 on end
+ end
end #PCIE6 WWAN
device ref pcie_rp8 on
# Enable SD Card PCIE 8 using clk 3
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