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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 19:
(2 comments)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/5fc37921_fcb3a3f1
PS19, Line 26: to
: reach at DSM
> Unless the hardware changed significantly, it's up to the graphics driver […]
In future platform, GMADR is replaced by LMEMBAR which is fixed map to DSM/GSM.
There is document 643504(FAS) mention it.
GTT size is "fixed" at 8MB(which it is WIP to update in external document).
https://review.coreboot.org/c/coreboot/+/61389/comment/0a0b7f1c_136477f1
PS19, Line 29: GTT_SIZE
> DSM used to mean the space of system DRAM that is pre-allocated for graphics, […]
Yes, the hardware process behind BAR 2(0x18) is changed in future platform. It forward to DSM/GSM while access BAR 2.
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Change subject: drivers/i2c/tpm/cr50: Add support to get cr50 firmware version
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
This is duplicating a ton of logic. Could you find a way to factor out the common parts so we don't need to maintain them twice? Maybe we should make a drivers/tpm/cr50.c or something like that to keep some common routines that are needed for both interfaces.
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
Patch Set 5:
(2 comments)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/61162/comment/d0860d77_23d74987
PS5, Line 3608: #define PCI_DEVICE_ID_INTEL_ADP_M_I2C0 0x54e8
ADL-N has also same id for I2C0-I2C3, why not change these?
https://review.coreboot.org/c/coreboot/+/61162/comment/eb66ab6c_0544ab55
PS5, Line 3683: #define PCI_DEVICE_ID_INTEL_ADP_M_UART3 0x54da
Same here for UART3
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 20:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61259/comment/8b6d7fe2_69e96f6f
PS20, Line 14: BRANCH
Add a new line between this and the Signed-Off-By
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
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Patch Set 20: Code-Review+2
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 20:
(2 comments)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/c44a52da_055ee34f
PS18, Line 159: if (clk_req == CLK_DISABLE || clk_req == CLK_ENABLE)
: continue;
> Why do we bail early?
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/5284a2fd_018947f7
PS18, Line 200: }
> Should we also check for the case where `pci_device->enabled` and the clk requests don't match?
Done
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