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Change subject: mb/google/brya: Create kinox variant
......................................................................
mb/google/brya: Create kinox variant
Create the kinox variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:215049181
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KINOX
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
Change-Id: I68cac421f6299a5f82f2ab51633173648c993060
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/kinox/include/variant/ec.h
A src/mainboard/google/brya/variants/kinox/include/variant/gpio.h
A src/mainboard/google/brya/variants/kinox/overridetree.cb
5 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61789/2
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Change subject: mb/google/brya/variants/primus: add dram part id
......................................................................
mb/google/brya/variants/primus: add dram part id
This change adds mem_parts_uesd.txt that contains the new memory parts
used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc
generated by gen_part_id using mem_parts_used.txt.
BUG=b:218415732
Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com>
Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693
---
M src/mainboard/google/brya/variants/primus/memory/Makefile.inc
M src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt
3 files changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61788/2
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Hello build bot (Jenkins), Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Alan Huang,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/brya/var/brask: Enable ASPM of RTL8125
......................................................................
mb/google/brya/var/brask: Enable ASPM of RTL8125
Brask cannot pass powerd_dbus_suspend test because the NIC does not
enter ASPM L1.2.
Here we add "enable_aspm_l1_2" in devicetree for RTL8125 to enable
ASPM L1.2.
BUG=b:204309459
BRANCH=None
TEST=emerge and test with command powerd_dbus_suspend
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80
---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/61268/5
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Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, Alan Huang,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
drivers/net/r8168: Add ASPM control mechanism
Add a new configuration parameter "enable_aspm_l1_2".
Write value 0xe059000f to register offset 0xb0 to allow kernel driver to
enable ASPM L1.2.
Use Kconfig "PCIEXP_ASPM" and "enable_aspm_l1_2" to decide whether to
enable ASPM L1.2.
BUG=b:204309459
TEST=emerge and test if the driver can read the correct value
Change-Id: I944dbf04d3ca19df4de224540bee538bff4d1f12
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
---
M src/drivers/net/chip.h
M src/drivers/net/r8168.c
2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/61267/5
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61720 )
Change subject: drivers/i2c/tpm/cr50: Add support to get cr50 firmware version
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> This is duplicating a ton of logic. […]
Yeah... I probably should have done that in the first place, I'll fix that.
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Change subject: Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Adjust CSE RO and Data partition in the CSE region
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61728/comment/700045f1_0f271b23
PS1, Line 14: stitch method and revert these changes of partition size.
> Please remove the trailing space.
Done
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