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Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@Jonathan/Amos, Ping! if you can review this CL.
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
Patch Set 6: Code-Review+2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61792 )
Change subject: drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
......................................................................
drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let FSP conditionally execute FSP Notify Phase APIs
unless SoC users overrides (with `default n`) those configs to run
native coreboot implementation as part of the `.final` ops.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/notify.c
2 files changed, 29 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/61792/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 2992b4f..4b3213c 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -310,41 +310,46 @@
SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
execute FspMultiPhaseSiInit() API.
-config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
- bool
+config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+ bool "Perform Notify Phase (Post PCI enumeration) by FSP"
+ default y
help
The FSP API is used to notify the FSP about different phases in the boot process.
The current FSP specification supports three notify phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
- Select this on a platform where you want to skip calling FSP Notify
- `Post PCI enumeration` API. Instead use coreboot native implementations
+ This option allows FSP to execute Notify Phase API (Post PCI enumeration).
+ SoC users can override this config to use coreboot native implementations
+ to perform the required lock down and chipset register configuration prior
+ to executing any 3rd-party code during PCI enumeration (i.e. Option ROM).
+
+config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
+ bool "Perform Notify Phase (Ready to Boot) by FSP"
+ default y
+ help
+ The FSP API is used to notify the FSP about different phases in the boot process.
+ The current FSP specification supports three notify phases:
+ - Post PCI enumeration
+ - Ready to Boot
+ - End of Firmware
+ This option allows FSP to execute Notify Phase API (Ready to Boot).
+ SoC users can override this config to use coreboot native implementations
to perform the required lock down and chipset register configuration prior
boot to payload.
-config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
- bool
+config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+ bool "Perform Notify Phase (End of Firmware) by FSP"
+ default y
help
The FSP API is used to notify the FSP about different phases in the boot process.
The current FSP specification supports three notify phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
- Select this on a platform where you want to skip calling FSP Notify `Ready to Boot`
- API. Instead use coreboot native implementations to perform the required lock down
- and chipset register configuration prior boot to payload.
-
-config SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
- bool
- help
- The FSP API is used to notify the FSP about different phases in the boot process.
- The current FSP specification supports three notify phases:
- - Post PCI enumeration
- - Ready to Boot
- - End of Firmware
- Select this on a platform where you want to skip calling FSP Notify `End of Firmware`
- API. Instead use coreboot native implementations to perform the required lock down
- and chipset register configuration prior boot to payload.
+ This option allows FSP to execute Notify Phase API (End of Firmware).
+ SoC users can override this config to use coreboot native implementations
+ to perform the required lock down and chipset register configuration prior
+ boot to payload.
endif
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 36b538f..30d61c9 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -20,7 +20,7 @@
static const struct fsp_notify_phase_data notify_data[] = {
{
.notify_phase = AFTER_PCI_ENUM,
- .skip = CONFIG(SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM),
+ .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
.post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
.timestamp_before = TS_FSP_BEFORE_ENUMERATE,
@@ -28,7 +28,7 @@
},
{
.notify_phase = READY_TO_BOOT,
- .skip = CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT),
+ .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
.post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
.timestamp_before = TS_FSP_BEFORE_FINALIZE,
@@ -36,7 +36,7 @@
},
{
.notify_phase = END_OF_FIRMWARE,
- .skip = CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
+ .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
.post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
.timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
Patch Set 6:
(2 comments)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/61162/comment/d1d967c7_92d61b87
PS5, Line 3608: #define PCI_DEVICE_ID_INTEL_ADP_M_I2C0 0x54e8
> ADL-N has also same id for I2C0-I2C3, why not change these?
Ack
https://review.coreboot.org/c/coreboot/+/61162/comment/7029c5aa_50feb04e
PS5, Line 3683: #define PCI_DEVICE_ID_INTEL_ADP_M_UART3 0x54da
> Same here for UART3
Ack
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Change subject: mb/google/nissa: Set half_populated true
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/nissa/memory.c:
https://review.coreboot.org/c/coreboot/+/61764/comment/ead715a5_fa648a53
PS3, Line 100: ADL-N only has a single memory channel.
> Could you please update this comment with a brief explanation?
Done
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Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/61791 )
Change subject: Documentation: Add GSoC info page
......................................................................
Documentation: Add GSoC info page
Work in progress.
Initially copied from https://www.coreboot.org/GSoC.
Change-Id: I5c21d026118cba571dc6b817e89cc4da296a1799
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
A Documentation/contributing/gsoc.md
M Documentation/index.md
2 files changed, 218 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/61791/2
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Attention is currently required from: Bora Guvendik, Selma Bensaid, Paul Menzel, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P, Patrick Rudolph.
Hello Bora Guvendik, build bot (Jenkins), Kangheui Won, Selma Bensaid, Tim Wawrzynczak, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61162
to look at the new patch set (#6).
Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and
use them for Alder Lake-N platform.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/uart/uart.c
11 files changed, 130 insertions(+), 128 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61162/6
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Rizwan Qureshi has uploaded a new patch set (#5) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/61764 )
Change subject: mb/google/nissa: Set half_populated true
......................................................................
mb/google/nissa: Set half_populated true
Alder Lake N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.
Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.
Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/nissa/memory.c
1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/61764/5
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Change subject: mb/google/nissa: Set half_populated true
......................................................................
mb/google/nissa: Set half_populated true
Alder Lake N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.
Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.
Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/nissa/memory.c
1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/61764/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e
Gerrit-Change-Number: 61764
Gerrit-PatchSet: 4
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