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Hello Tim Wawrzynczak, Wisley Chen,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/agah: Update Aux settings
......................................................................
mb/google/brya/var/agah: Update Aux settings
Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
Add the TcssAuxOri and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
when the cable is flipped
Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/agah/overridetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61795/2
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Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61795 )
Change subject: mb/google/brya/var/agah: Add TcssAuxOri settings for Port 0
......................................................................
mb/google/brya/var/agah: Add TcssAuxOri settings for Port 0
Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
Set the TcssAuxOri and add "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
when the cable is flipped
Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/agah/overridetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61795/1
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index 3856df2..f890582 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -1,5 +1,4 @@
chip soc/intel/alderlake
- register "SaGv" = "SaGv_Enabled"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -31,6 +30,10 @@
},
}"
+ register "SaGv" = "SaGv_Enabled"
+ register "TcssAuxOri" = "1"
+ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
register "usb2_ports[4]" = "USB2_PORT_EMPTY" #
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61649 )
Change subject: soc/intel/*/pmc: Add `finalize` operation for pmc
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61649/comment/31df39cd_ad62eb99
PS6, Line 11: APIs i.e. Ready
> NIT - please add two comments : […]
Ack
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61649
to look at the new patch set (#8).
Change subject: soc/intel/*/pmc: Add `finalize` operation for pmc
......................................................................
soc/intel/*/pmc: Add `finalize` operation for pmc
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247
---
M src/soc/intel/alderlake/pmc.c
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/elkhartlake/pmc.c
M src/soc/intel/icelake/pmc.c
M src/soc/intel/jasperlake/pmc.c
M src/soc/intel/tigerlake/pmc.c
7 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61649/8
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Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61793 )
Change subject: cpu/x86/lapic: Fix SMP=n case with LEGACY_SMP_INIT
......................................................................
cpu/x86/lapic: Fix SMP=n case with LEGACY_SMP_INIT
Fix regression after commit 9ec7227c9b
cpu/x86/lapic: Move LAPIC configuration to MP init
The call to disable_lapic() got removed and with asus/p2b
SeaBIOS payload was unable to load kernel.
The combination of entering SeaBIOS payload with an
enabled lapic but not having programmed LAPIC_LVT0
for DELIVERY_MODE_EXTINT apparently disconnects i8259
PIC interrupt delivery pin.
Change-Id: If51e5d65153a02ac7af191e7897c04bd4e298006
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/lapic/lapic_cpu_init.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/61793/1
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 837d32f..2cb8459 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -384,6 +384,8 @@
if (is_smp_boot()) {
enable_lapic();
setup_lapic_interrupts();
+ } else {
+ disable_lapic();
}
/* Get the device path of the boot CPU */
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Change subject: soc/intel/*/pmc: Add `finalize` operation for pmc
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/pmc.c:
https://review.coreboot.org/c/coreboot/+/61649/comment/ca4f5b0d_f75feb19
PS6, Line 182: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
> do we even really need the Kconfig here? I don't think there would be any harm in clearing the bits […]
Ack
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61649
to look at the new patch set (#7).
Change subject: soc/intel/*/pmc: Add `finalize` operation for pmc
......................................................................
soc/intel/*/pmc: Add `finalize` operation for pmc
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247
---
M src/soc/intel/alderlake/pmc.c
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/elkhartlake/pmc.c
M src/soc/intel/icelake/pmc.c
M src/soc/intel/jasperlake/pmc.c
M src/soc/intel/tigerlake/pmc.c
7 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61649/7
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Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61776 )
Change subject: Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
......................................................................
Patch Set 1: Code-Review+2
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
soc/intel/common/cse: Add `finalize` operation for CSE
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects all required configs:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/26
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