Attention is currently required from: Hung-Te Lin, Rex-BC Chen.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61796 )
Change subject: soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Not verified on a device yet.
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Change subject: src/cpu/power9: add file structure for power9, implement SCOM access
......................................................................
Patch Set 18: Code-Review+2
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Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, EricR Lai.
Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Lean Sheng Tan, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60406
to look at the new patch set (#22).
Change subject: soc/intel/alderlake: Skip FSP Notify APIs
......................................................................
soc/intel/alderlake: Skip FSP Notify APIs
SoC overrides relevant Kconfigs as below with `default n`:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.
Additionally, created a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
2 files changed, 16 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/60406/22
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61776 )
Change subject: Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
......................................................................
Patch Set 1: Code-Review+1
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Hello Tim Wawrzynczak, Wisley Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61795
to look at the new patch set (#3).
Change subject: mb/google/brya/var/agah: Update Aux settings
......................................................................
mb/google/brya/var/agah: Update Aux settings
Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/agah/overridetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61795/3
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