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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61802 )
Change subject: nb/intel/i945/rcven.c: Use enum cb_err for static functions
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Thx
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Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/61801 )
Change subject: acpi: Use ACPI macros to configure USB port _PLD object
......................................................................
acpi: Use ACPI macros to configure USB port _PLD object
This patch adds two ACPI macros for USB port A and C _PLD object
configuration as:
1. ACPI_PLD_TYPE_A
2. ACPI_PLD_TYPE_C
The configurable parameters are
- Panel, Port is exposed on which face of a panel.
- Horizontal, Horizontal position on the panel where the device
connection point resides.
- Group
- Token, Unique numerical value identifying a group.
- Position, Identifies this device connection point’s position
in the group (i.e. 1st, 2nd).
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6
---
M src/include/acpi/acpi_pld.h
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/61801/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61801 )
Change subject: acpi: Use ACPI macros to configure USB port _PLD object
......................................................................
Patch Set 1:
(1 comment)
File src/include/acpi/acpi_pld.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140511):
https://review.coreboot.org/c/coreboot/+/61801/comment/c1d2ffb5_e83bf221
PS1, Line 71: #define ACPI_PLD_TYPE_A(__panel, __horiz, __grp) \
please, no space before tabs
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61718 )
Change subject: drivers/i2c/tpm/cr50: Remove unused `chip` function arguments
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/61718/comment/c119029d_3a118d08
PS2, Line 62: static int
out of topic:
I'd use "static enum cb_err " ...
return CB_ERR or CB_SUCCESS
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61737 )
Change subject: util/inteltool: Actually read SATA init data from SIRD
......................................................................
Patch Set 4: Code-Review+2
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Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61605 )
Change subject: mb/google/brya/var/nivviks: Initialise overridetree
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/61605/comment/073601fb_f9c43a07
PS1, Line 10: SaGv_Enabled
> Probably, but good to double check. […]
System is table with SaGv enabled in the current FSP version.
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Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61776 )
Change subject: Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
......................................................................
Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
This reverts commit ceaf959678905f44a54a116f37bd15acab5d4608.
The AMD Picasso SoC doesn't support x2APIC and neither advertises the
presence of its support via bit 21 in EAX of CPUID leaf 1 nor has the
bit 10 in the APIC base address MSR 0x1b set, but it does have 0xd CPUID
leaves, so just checking for the presence of that CPUID leaf isn't
sufficient to be sure that EDX of the CPUID leaf 0xb will contain a
valid APIC ID.
In the case of Picasso EDX of the CPUID leaf 0xb returns 0 for all cores
which causes coreboot to get stuck somewhere at the end of MP init.
I'm not 100% sure if we should additionally check bit 21 in EAX of CPUID
function 1 is set instead of adding back the is_x2apic_mode check.
TEST=Mandolin with a Picasso SoC boots again.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If1e3c55ce2d048b14c08e06bb79810179a87993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61776
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Christian Walter <christian.walter(a)9elements.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/smm/smm_stub.S
M src/include/cpu/x86/lapic.h
2 files changed, 13 insertions(+), 8 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kyösti Mälkki: Looks good to me, approved
Raul Rangel: Looks good to me, approved
Angel Pons: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
Christian Walter: Looks good to me, approved
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 25a35aa..c83839c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -101,25 +101,30 @@
* the OS can manipulate the APIC id use the non-changing cpuid result
* for APIC id (eax). A table is used to handle a discontiguous
* APIC id space. */
+apic_id:
+ mov $LAPIC_BASE_MSR, %ecx
+ rdmsr
+ and $LAPIC_BASE_X2APIC_ENABLED, %eax
+ cmp $LAPIC_BASE_X2APIC_ENABLED, %eax
+ jne xapic
- mov $0, %eax
- cpuid
- cmp $0xb, %eax
- jc 1f
+x2apic:
mov $0xb, %eax
mov $0, %ecx
cpuid
mov %edx, %eax
- jmp 2f
-1:
+ jmp apicid_end
+
+xapic:
mov $1, %eax
cpuid
mov %ebx, %eax
shr $24, %eax
-2:
+apicid_end:
mov $(apic_to_cpu_num), %ebx
xor %ecx, %ecx
+
1:
cmp (%ebx, %ecx, 2), %ax
je 1f
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 7006dbc..c509e61 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -126,7 +126,7 @@
static __always_inline unsigned int initial_lapicid(void)
{
uint32_t lapicid;
- if (cpuid_get_max_func() >= 0xb)
+ if (is_x2apic_mode() && cpuid_get_max_func() >= 0xb)
lapicid = cpuid_ext(0xb, 0).edx;
else
lapicid = cpuid_ebx(1) >> 24;
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