Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61714 )
Change subject: libpayload/libc/coreboot: Fix CBFS MCache size
......................................................................
libpayload/libc/coreboot: Fix CBFS MCache size
CBFS MCache size was assigned a value of the coreboot tables entry size
instead of the MCache size.
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I8a8c3a10c6032121b4c5246d53d2643742968c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61714
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M payloads/libpayload/libc/coreboot.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Julius Werner: Looks good to me, approved
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 79a382b..72d7664 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -230,11 +230,11 @@
break;
case CBMEM_ID_CBFS_RO_MCACHE:
info->cbfs_ro_mcache_offset = cbmem_entry->address;
- info->cbfs_ro_mcache_size = cbmem_entry->size;
+ info->cbfs_ro_mcache_size = cbmem_entry->entry_size;
break;
case CBMEM_ID_CBFS_RW_MCACHE:
info->cbfs_rw_mcache_offset = cbmem_entry->address;
- info->cbfs_rw_mcache_size = cbmem_entry->size;
+ info->cbfs_rw_mcache_size = cbmem_entry->entry_size;
break;
case CBMEM_ID_CONSOLE:
info->cbmem_cons = cbmem_entry->address;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8a8c3a10c6032121b4c5246d53d2643742968c09
Gerrit-Change-Number: 61714
Gerrit-PatchSet: 2
Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57784 )
Change subject: device: Add pciexp_find_next_extended_cap function
......................................................................
device: Add pciexp_find_next_extended_cap function
Some PCIe devices have extended capability lists that contain
multiples instances of the same capability. This patch provides a
function similar to pciexp_find_extended_cap that can be used to
search through multiple instances of the same capability by returning
the offset of the next extended capability of the given type following
the passed-in offset. The base functionality of searching for a given
capability from an offset is extracted to a local helper function and
both pciexp_find_extended_cap and pciexp_find_next_extended_cap use
this helper.
Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57784
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/device/pciexp_device.c
M src/include/device/pciexp.h
2 files changed, 23 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index e0b3544..c525301 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -8,29 +8,39 @@
#include <device/pci_ops.h>
#include <device/pciexp.h>
-unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap)
+static unsigned int pciexp_get_ext_cap_offset(const struct device *dev, unsigned int cap,
+ unsigned int offset)
{
- unsigned int this_cap_offset, next_cap_offset;
- unsigned int this_cap, cafe;
-
- this_cap_offset = PCIE_EXT_CAP_OFFSET;
+ unsigned int this_cap_offset = offset;
+ unsigned int next_cap_offset, this_cap, cafe;
do {
this_cap = pci_read_config32(dev, this_cap_offset);
- next_cap_offset = this_cap >> 20;
- this_cap &= 0xffff;
cafe = pci_read_config32(dev, this_cap_offset + 4);
- cafe &= 0xffff;
- if (this_cap == cap)
+ if ((this_cap & 0xffff) == cap) {
return this_cap_offset;
- else if (cafe == cap)
+ } else if ((cafe & 0xffff) == cap) {
return this_cap_offset + 4;
- else
+ } else {
+ next_cap_offset = this_cap >> 20;
this_cap_offset = next_cap_offset;
+ }
} while (next_cap_offset != 0);
return 0;
}
+unsigned int pciexp_find_next_extended_cap(const struct device *dev, unsigned int cap,
+ unsigned int pos)
+{
+ const unsigned int next_cap_offset = pci_read_config32(dev, pos) >> 20;
+ return pciexp_get_ext_cap_offset(dev, cap, next_cap_offset);
+}
+
+unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap)
+{
+ return pciexp_get_ext_cap_offset(dev, cap, PCIE_EXT_CAP_OFFSET);
+}
+
/*
* Re-train a PCIe link
*/
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index a72c2ec..30c2a54 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -31,6 +31,8 @@
extern struct device_operations default_pciexp_hotplug_ops_bus;
unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap);
+unsigned int pciexp_find_next_extended_cap(const struct device *dev, unsigned int cap,
+ unsigned int offset);
static inline bool pciexp_is_downstream_port(int type)
{
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa
Gerrit-Change-Number: 57784
Gerrit-PatchSet: 6
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com>
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61723 )
Change subject: lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61723/comment/63303449_ef626de7
PS1, Line 9: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'
> Please use that as the commit message summary.
Ack
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Gerrit-Change-Id: Ie20a2c35afc2b849396ddb023b99aab33836b8de
Gerrit-Change-Number: 61723
Gerrit-PatchSet: 2
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-Comment-Date: Thu, 10 Feb 2022 11:53:39 +0000
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Attention is currently required from: HAOUAS Elyes.
Hello build bot (Jenkins), Paul Menzel, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61723
to look at the new patch set (#2).
Change subject: lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'
......................................................................
lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'
Change-Id: Ie20a2c35afc2b849396ddb023b99aab33836b8de
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/lib/device_tree.c
1 file changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61723/2
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61802 )
Change subject: nb/intel/i945/rcven.c: Use enum cb_err for static functions
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/intel/i945/rcven.c:
https://review.coreboot.org/c/coreboot/+/61802/comment/ef49a1b3_e78dbe6f
PS1, Line 106: C0WL0REOST
C{0,1}WL1REOST, C{0,1}WL2REOST and C{0,1}WL3REOST are missing, right ?
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/60338 )
Change subject: soc/mediatek/mt8186: Add SPM firmware
......................................................................
Patch Set 1:
(1 comment)
File soc/mediatek/mt8186/spm_firmware.bin:
PS1:
> Rex, I noticed that there are trailing spaces (0x20) at the end of the blob. […]
I think it's not a good idea to change this.
This image is provided by MT8186 SPM hardware designer.
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